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1. 发明申请

US20070131159A1 Method for epitaxial growth with selectivity 审中-公开
标题翻译：用选择性外延生长的方法
公开(公告)号：US20070131159A1
公开(公告)日：2007-06-14
申请号：US11638373
申请日：2006-12-14
申请人： Young-Pil Kim , Jin Kim , Min-Gu Kang , Yu-Gyun Shin , Jong-Wook Lee
发明人： Young-Pil Kim , Jin Kim , Min-Gu Kang , Yu-Gyun Shin , Jong-Wook Lee
IPC分类号： C30B13/00 , C30B19/00 , C30B28/08 , C30B23/00
CPC分类号： C30B25/18 , C30B29/06 , C30B29/08 , C30B33/12
摘要： A method for growing an epitaxial layer includes obtaining a semiconductor substrate having a plurality of insulating and conductive surfaces, adsorbing a first source gas into the plurality of conductive surfaces to grow a first epitaxial layer thereon, such that the first epitaxial layer has lateral portions overhanging the insulating surfaces, etching the first epitaxial layer to form an etched epitaxial layer, such that the etched epitaxial layer has curved surfaces, and supplying a second source gas to trigger additional epitaxial growth in the etched epitaxial layer.
摘要翻译：一种用于生长外延层的方法包括获得具有多个绝缘和导电表面的半导体衬底，将第一源气体吸附到多个导电表面中以在其上生长第一外延层，使得第一外延层具有悬垂的侧向部分蚀刻第一外延层以形成蚀刻的外延层，使得蚀刻的外延层具有弯曲表面，并且提供第二源气体以触发蚀刻的外延层中的另外的外延生长。

2. 发明申请

US20060189058A1 Fin type field effect transistors and methods of manufacturing the same 有权
标题翻译：鳍式场效应晶体管及其制造方法
公开(公告)号：US20060189058A1
公开(公告)日：2006-08-24
申请号：US11359000
申请日：2006-02-22
申请人： Jong-Wook Lee , Deok-Hyung Lee , Min-Gu Kang , Yu-Gyun Shin
发明人： Jong-Wook Lee , Deok-Hyung Lee , Min-Gu Kang , Yu-Gyun Shin
IPC分类号： H01L21/8234 , H01L29/76
CPC分类号： H01L29/78618 , H01L29/66545 , H01L29/66795 , H01L29/785
摘要： A fin type field effect transistor includes a semiconductor substrate, an active fin, a first hard mask layer pattern, a gate insulation layer pattern, a first conductive layer pattern, and source/drain regions. The active fin includes a semiconductor material and is formed on the substrate and extends in a direction away from a major surface of the substrate. The first hard mask layer pattern is formed on a distal surface of the active fin from the substrate. The gate insulation layer is formed on a sidewall portion of the active fin. The first conductive layer pattern includes a metal silicide and is formed on surfaces of the substrate and the gate insulation layer pattern, and on a sidewall of the first hard mask pattern. The source/drain regions are formed in the active fin on opposite sides of the first conductive layer pattern.
摘要翻译：鳍型场效应晶体管包括半导体衬底，有源鳍，第一硬掩模层图案，栅极绝缘层图案，第一导电层图案和源极/漏极区域。活性鳍片包括半导体材料，并且形成在基底上并沿远离基底的主表面的方向延伸。第一硬掩模层图案形成在有源鳍片的远离表面上的基底上。栅极绝缘层形成在有源鳍片的侧壁部分上。第一导电层图案包括金属硅化物，并且形成在基板和栅极绝缘层图案的表面上，以及在第一硬掩模图案的侧壁上。源极/漏极区域形成在第一导电层图案的相对侧上的有源鳍片中。

3. 发明申请

US20060118876A1 Fin field effect transistor and method of manufacturing the same 有权
标题翻译： Fin场效应晶体管及其制造方法
公开(公告)号：US20060118876A1
公开(公告)日：2006-06-08
申请号：US11292261
申请日：2005-11-30
申请人： Deok-Hyung Lee , Yu-Gyun Shin , Jong-Wook Lee , Min-Gu Kang
发明人： Deok-Hyung Lee , Yu-Gyun Shin , Jong-Wook Lee , Min-Gu Kang
IPC分类号： H01L21/338 , H01L29/76
CPC分类号： H01L29/7851 , H01L29/66795 , H01L29/7854
摘要： In a fin field effect transistor (FET), an active pattern protrudes in a vertical direction from a substrate and extends across the substrate in a first horizontal direction. A first silicon nitride pattern is formed on the active pattern, and a first oxide pattern and a second silicon nitride pattern are sequentially formed on the substrate and on a sidewall of a lower portion of the active pattern. A device isolation layer is formed on the second silicon nitride pattern, and a top surface of the device isolation layer is coplanar with top surfaces of the oxide pattern and the second silicon nitride pattern. A buffer pattern having an etching selectivity with respect to the second silicon nitride pattern is formed between the first oxide pattern and the second silicon nitride pattern. Internal stresses that can be generated in sidewalls of the active pattern are sufficiently released and an original shape of the first silicon nitride pattern remains unchanged, thereby improving electrical characteristics of the fin FET.
摘要翻译：在鳍状场效应晶体管（FET）中，有源图案在垂直方向上从基板突出，并且在第一水平方向上延伸穿过基板。第一氮化硅图案形成在有源图案上，并且第一氧化物图案和第二氮化硅图案依次形成在衬底上和活性图案的下部的侧壁上。在第二氮化硅图案上形成器件隔离层，器件隔离层的顶表面与氧化物图案和第二氮化硅图案的顶表面共面。在第一氧化物图案和第二氮化硅图案之间形成具有相对于第二氮化硅图案的蚀刻选择性的缓冲图案。可以在有源图案的侧壁中产生的内部应力被充分地释放，并且第一氮化硅图案的原始形状保持不变，从而改善了鳍式FET的电特性。

4. 发明申请

US20060081895A1 Semiconductor device having fin transistor and planar transistor and associated methods of manufacture 有权
公开(公告)号：US20060081895A1
公开(公告)日：2006-04-20
申请号：US11244136
申请日：2005-10-06
申请人： Deok-Huyng Lee , Yu-Gyun Shin , Jong-Wook Lee , Min-Gu Kang
发明人： Deok-Huyng Lee , Yu-Gyun Shin , Jong-Wook Lee , Min-Gu Kang
IPC分类号： H01L29/76
CPC分类号： H01L29/7851 , H01L21/823431 , H01L21/84 , H01L27/1203 , H01L29/66795
摘要： Disclosed is a fin transistor and a planar transistor and a method of forming the same. The fin transistor and the planar transistor are formed to have gate electrodes with similar thicknesses by selectively recessing a semiconductor substrate in a planar region where the planar transistor is formed.

5. 发明申请

US20080093674A1 FIN FIELD EFFECT TRANSISTOR AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译： FIN场效应晶体管及其制造方法
公开(公告)号：US20080093674A1
公开(公告)日：2008-04-24
申请号：US11952676
申请日：2007-12-07
申请人： Deok-Hyung Lee , Yu-Gyun Shin , Jong-Wook Lee , Min-Gu Kang
发明人： Deok-Hyung Lee , Yu-Gyun Shin , Jong-Wook Lee , Min-Gu Kang
IPC分类号： H01L29/78
CPC分类号： H01L29/7851 , H01L29/66795 , H01L29/7854
摘要： In a fin field effect transistor (FET), an active pattern protrudes in a vertical direction from a substrate and extends across the substrate in a first horizontal direction. A first silicon nitride pattern is formed on the active pattern, and a first oxide pattern and a second silicon nitride pattern are sequentially formed on the substrate and on a sidewall of a lower portion of the active pattern. A device isolation layer is formed on the second silicon nitride pattern, and a top surface of the device isolation layer is coplanar with top surfaces of the oxide pattern and the second silicon nitride pattern. A buffer pattern having an etching selectivity with respect to the second silicon nitride pattern is formed between the first oxide pattern and the second silicon nitride pattern. Internal stresses that can be generated in sidewalls of the active pattern are sufficiently released and an original shape of the first silicon nitride pattern remains unchanged, thereby improving electrical characteristics of the fin FET.
摘要翻译：在鳍状场效应晶体管（FET）中，有源图案在垂直方向上从基板突出，并且在第一水平方向上延伸穿过基板。第一氮化硅图案形成在有源图案上，并且第一氧化物图案和第二氮化硅图案依次形成在衬底上和活性图案的下部的侧壁上。在第二氮化硅图案上形成器件隔离层，器件隔离层的顶表面与氧化物图案和第二氮化硅图案的顶表面共面。在第一氧化物图案和第二氮化硅图案之间形成具有相对于第二氮化硅图案的蚀刻选择性的缓冲图案。可以在有源图案的侧壁中产生的内部应力被充分地释放，并且第一氮化硅图案的原始形状保持不变，从而改善了鳍式FET的电特性。

6. 发明授权

US07652340B2 Fin field effect transistor and method of manufacturing the same 有权
标题翻译： Fin场效应晶体管及其制造方法
公开(公告)号：US07652340B2
公开(公告)日：2010-01-26
申请号：US11952676
申请日：2007-12-07
申请人： Deok-Hyung Lee , Yu-Gyun Shin , Jong-Wook Lee , Min-Gu Kang
发明人： Deok-Hyung Lee , Yu-Gyun Shin , Jong-Wook Lee , Min-Gu Kang
IPC分类号： H01L29/78
CPC分类号： H01L29/7851 , H01L29/66795 , H01L29/7854
摘要： In a fin field effect transistor (FET), an active pattern protrudes in a vertical direction from a substrate and extends across the substrate in a first horizontal direction. A first silicon nitride pattern is formed on the active pattern, and a first oxide pattern and a second silicon nitride pattern are sequentially formed on the substrate and on a sidewall of a lower portion of the active pattern. A device isolation layer is formed on the second silicon nitride pattern, and a top surface of the device isolation layer is coplanar with top surfaces of the oxide pattern and the second silicon nitride pattern. A buffer pattern having an etching selectivity with respect to the second silicon nitride pattern is formed between the first oxide pattern and the second silicon nitride pattern. Internal stresses that can be generated in sidewalls of the active pattern are sufficiently released and an original shape of the first silicon nitride pattern remains unchanged, thereby improving electrical characteristics of the fin FET.
摘要翻译：在鳍状场效应晶体管（FET）中，有源图案在垂直方向上从基板突出，并且在第一水平方向上延伸穿过基板。第一氮化硅图案形成在有源图案上，并且第一氧化物图案和第二氮化硅图案依次形成在衬底上和活性图案的下部的侧壁上。在第二氮化硅图案上形成器件隔离层，器件隔离层的顶表面与氧化物图案和第二氮化硅图案的顶表面共面。在第一氧化物图案和第二氮化硅图案之间形成具有相对于第二氮化硅图案的蚀刻选择性的缓冲图案。可以在有源图案的侧壁中产生的内部应力被充分地释放，并且第一氮化硅图案的原始形状保持不变，从而改善了鳍式FET的电特性。

7. 发明授权

US07501674B2 Semiconductor device having fin transistor and planar transistor and associated methods of manufacture 有权
标题翻译：具有鳍式晶体管和平面晶体管的半导体器件及其制造方法
公开(公告)号：US07501674B2
公开(公告)日：2009-03-10
申请号：US11244136
申请日：2005-10-06
申请人： Deok-Hyung Lee , Yu-Gyun Shin , Jong-Wook Lee , Min-Gu Kang
发明人： Deok-Hyung Lee , Yu-Gyun Shin , Jong-Wook Lee , Min-Gu Kang
IPC分类号： H01L21/00
CPC分类号： H01L29/7851 , H01L21/823431 , H01L21/84 , H01L27/1203 , H01L29/66795
摘要： Disclosed is a fin transistor and a planar transistor and a method of forming the same. The fin transistor and the planar transistor are formed to have gate electrodes with similar thicknesses by selectively recessing a semiconductor substrate in a planar region where the planar transistor is formed.
摘要翻译：公开了鳍式晶体管和平面晶体管及其形成方法。通过在形成平面晶体管的平面区域中选择性地凹入半导体衬底，将鳍状晶体管和平面晶体管形成为具有相似厚度的栅电极。

8. 发明授权

US07442596B2 Methods of manufacturing fin type field effect transistors 有权
标题翻译：制造鳍式场效应晶体管的方法
公开(公告)号：US07442596B2
公开(公告)日：2008-10-28
申请号：US11359000
申请日：2006-02-22
申请人： Jong-Wook Lee , Deok-Hyung Lee , Min-Gu Kang , Yu-Gyun Shin
发明人： Jong-Wook Lee , Deok-Hyung Lee , Min-Gu Kang , Yu-Gyun Shin
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L29/78618 , H01L29/66545 , H01L29/66795 , H01L29/785
摘要： A fin type field effect transistor includes a semiconductor substrate, an active fin, a first hard mask layer pattern, a gate insulation layer pattern, a first conductive layer pattern, and source/drain regions. The active fin includes a semiconductor material and is formed on the substrate and extends in a direction away from a major surface of the substrate. The first hard mask layer pattern is formed on a distal surface of the active fin from the substrate. The gate insulation layer is formed on a sidewall portion of the active fin. The first conductive layer pattern includes a metal silicide and is formed on surfaces of the substrate and the gate insulation layer pattern, and on a sidewall of the first hard mask pattern. The source/drain regions are formed in the active fin on opposite sides of the first conductive layer pattern.
摘要翻译：鳍型场效应晶体管包括半导体衬底，有源鳍，第一硬掩模层图案，栅极绝缘层图案，第一导电层图案和源极/漏极区域。活性鳍片包括半导体材料，并且形成在基底上并沿远离基底的主表面的方向延伸。第一硬掩模层图案形成在有源鳍片的远离表面上的基底上。栅极绝缘层形成在有源鳍片的侧壁部分上。第一导电层图案包括金属硅化物，并且形成在基板和栅极绝缘层图案的表面上，以及在第一硬掩模图案的侧壁上。源极/漏极区域形成在第一导电层图案的相对侧上的有源鳍片中。

9. 发明授权

US07326608B2 Fin field effect transistor and method of manufacturing the same 有权
标题翻译： Fin场效应晶体管及其制造方法
公开(公告)号：US07326608B2
公开(公告)日：2008-02-05
申请号：US11292261
申请日：2005-11-30
申请人： Deok-Hyung Lee , Yu-Gyun Shin , Jong-Wook Lee , Min-Gu Kang
发明人： Deok-Hyung Lee , Yu-Gyun Shin , Jong-Wook Lee , Min-Gu Kang
IPC分类号： H01L21/8238
CPC分类号： H01L29/7851 , H01L29/66795 , H01L29/7854
摘要： In a fin field effect transistor (FET), an active pattern protrudes in a vertical direction from a substrate and extends across the substrate in a first horizontal direction. A first silicon nitride pattern is formed on the active pattern, and a first oxide pattern and a second silicon nitride pattern are sequentially formed on the substrate and on a sidewall of a lower portion of the active pattern. A device isolation layer is formed on the second silicon nitride pattern, and a top surface of the device isolation layer is coplanar with top surfaces of the oxide pattern and the second silicon nitride pattern. A buffer pattern having an etching selectivity with respect to the second silicon nitride pattern is formed between the first oxide pattern and the second silicon nitride pattern. Internal stresses that can be generated in sidewalls of the active pattern are sufficiently released and an original shape of the first silicon nitride pattern remains unchanged, thereby improving electrical characteristics of the fin FET.
摘要翻译：在鳍状场效应晶体管（FET）中，有源图案在垂直方向上从基板突出，并且在第一水平方向上延伸穿过基板。第一氮化硅图案形成在有源图案上，并且第一氧化物图案和第二氮化硅图案依次形成在衬底上和活性图案的下部的侧壁上。在第二氮化硅图案上形成器件隔离层，器件隔离层的顶表面与氧化物图案和第二氮化硅图案的顶表面共面。在第一氧化物图案和第二氮化硅图案之间形成具有相对于第二氮化硅图案的蚀刻选择性的缓冲图案。可以在有源图案的侧壁中产生的内部应力被充分地释放，并且第一氮化硅图案的原始形状保持不变，从而改善了鳍式FET的电特性。

10. 发明申请

US20090239348A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090239348A1
公开(公告)日：2009-09-24
申请号：US12478345
申请日：2009-06-04
申请人： Sun-Ghil Lee , Young-Pil Kim , Yu-Gyun Shin , Jong-Wook Lee , Young-Eun Lee
发明人： Sun-Ghil Lee , Young-Pil Kim , Yu-Gyun Shin , Jong-Wook Lee , Young-Eun Lee
IPC分类号： H01L21/336
CPC分类号： C30B29/06 , C30B15/00
摘要： A semiconductor device formed on a strained silicon layer and a method of manufacturing such a semiconductor device are disclosed. In accordance with this invention, a first silicon germanium layer is formed on a single crystalline silicon substrate; a second silicon germanium layer is formed on the first silicon germanium layer, the second silicon germanium layer having a concentration of germanium in a range of about 1 percent by weight to about 15 percent by weight based on the total weight of the second silicon germanium layer; a strained silicon layer is formed on the second silicon germanium layer; an isolation layer is formed at a first portion of the strained silicon layer; a gate structure is formed on the strained silicon layer; and, source/drain regions are formed at second portions of the strained silicon layer adjacent to the gate structure to form a transistor.
摘要翻译：公开了一种形成在应变硅层上的半导体器件及其制造方法。根据本发明，在单晶硅衬底上形成第一硅锗层; 第二硅锗层形成在第一硅锗层上，第二硅锗层的锗浓度在约1重量％至约15重量％的范围内，基于第二硅锗层的总重量 ; 在第二硅锗层上形成应变硅层; 在应变硅层的第一部分处形成隔离层; 在应变硅层上形成栅极结构; 并且源极/漏极区域形成在与栅极结构相邻的应变硅层的第二部分处以形成晶体管。

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