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    • 8. 发明申请
    • Method of producing balanced data output
    • 产生平衡数据输出的方法
    • US20060244492A1
    • 2006-11-02
    • US11114130
    • 2005-04-26
    • Seong-Hoon Lee
    • Seong-Hoon Lee
    • H03K5/22
    • H03K5/04H03K5/135H03K5/26
    • Strobe signals are coupled to a phase detector which compares rising and falling edges of the respective strobe signals. If the phase detector determines that there is a mismatch, it outputs an UP or DOWN control signal to a control circuit. The control circuit then transmits the UP or DOWN control signal to edge adjusting circuits connected to each strobe and data stream between the flip flop and pre-driver. The edge adjusting then adds a delay to each respective strobe and data stream which incrementally compensates for the mismatch created by PVT variations. The process is repeated until the high and low data outputs are effectively matched, thereby maximizing the data eye.
    • 选通信号耦合到相位检测器,该相位检测器比较各个选通信号的上升沿和下降沿。 如果相位检测器确定存在不匹配,则向控制电路输出UP或DOWN控制信号。 然后,控制电路将UP或DOWN控制信号发送到连接到每个选通脉冲的边缘调整电路和触发器和预驱动器之间的数据流。 边缘调整然后对每个相应的选通和数据流添加一个延迟,增量地补偿由PVT变化产生的失配。 重复该过程,直到高和低数据输出被有效地匹配,从而使数据眼睛最大化。
    • 10. 发明申请
    • Clock generating circuit with multiple modes of operation
    • 具有多种工作模式的时钟发生电路
    • US20060176761A1
    • 2006-08-10
    • US11054885
    • 2005-02-09
    • Seong-Hoon Lee
    • Seong-Hoon Lee
    • G11C8/00
    • G11C7/1072G11C7/222H03L7/0812H03L7/095H03L7/0995
    • A clock generating circuit includes a phase comparison circuit that generates a delay control signal corresponding o the relative phases of an output clock signal and a reference clock signal. A voltage controlled delay circuit generates the delayed clock signal by inverting a signal applied to its input and delaying the signal by a delay that is determined by a delay control signal. A selection circuit couples either the reference clock signal or the delayed clock signal to the input of the voltage controlled delay circuit. When the reference clock signal is coupled to the input of the voltage controlled delay circuit, the clock generating circuit functions as a delay-lock loop. When the delayed clock signal is coupled to the input of the voltage controlled delay circuit, the voltage controlled delay circuit operates as a ring oscillator so that the clock generating circuit functions as a phase-lock loop.
    • 时钟发生电路包括相位比较电路,该相位比较电路产生对应于输出时钟信号和参考时钟信号的相对相位的延迟控制信号。 电压控制延迟电路通过反相施加到其输入的信号并延迟由延迟控制信号确定的延迟来产生延迟的时钟信号。 选择电路将参考时钟信号或延迟时钟信号耦合到电压控制延迟电路的输入端。 当参考时钟信号耦合到电压控制延迟电路的输入时,时钟发生电路用作延迟锁定环路。 当延迟时钟信号耦合到电压控制延迟电路的输入端时,电压控制延迟电路作为环形振荡器工作,使得时钟发生电路用作锁相环。