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1. 发明授权

US07791396B2 Semiconductor integrated circuit and semiconductor package module having the same 有权
标题翻译：具有相同的半导体集成电路和半导体封装模块
公开(公告)号：US07791396B2
公开(公告)日：2010-09-07
申请号：US11822268
申请日：2007-07-03
申请人： Young-Ju Kim , Kwan-Weon Kim
发明人： Young-Ju Kim , Kwan-Weon Kim
IPC分类号： H03L5/00
CPC分类号： H03K19/0016
摘要： A semiconductor integrated circuit includes a first clock pin controller that receives a mirror function signal and a test mode signal to generate a first input buffer control signal in response to the mirror function signal in a normal mode. A second clock pin controller receives the mirror function signal and the test mode signal to generate a second input buffer control signal, which is an inverted signal of the first input buffer control signal, in response to the mirror function signal in the normal mode. An input buffer unit generates output signals of first and second pins in response to the first input buffer control signal and the second input buffer control signal, respectively.
摘要翻译：半导体集成电路包括：第一时钟引脚控制器，其接收反射镜功能信号和测试模式信号，以响应正常模式下的镜像功能信号产生第一输入缓冲器控制信号。第二时钟引脚控制器响应于正常模式下的镜像功能信号，接收镜像功能信号和测试模式信号，以产生作为第一输入缓冲器控制信号的反相信号的第二输入缓冲器控制信号。输入缓冲单元分别响应于第一输入缓冲器控制信号和第二输入缓冲器控制信号产生第一和第二引脚的输出信号。

2. 发明申请

US20080225497A1 Semiconductor integrated circuit and semiconductor package module having the same 有权
标题翻译：具有相同的半导体集成电路和半导体封装模块
公开(公告)号：US20080225497A1
公开(公告)日：2008-09-18
申请号：US11822268
申请日：2007-07-03
申请人： Young Ju Kim , Kwan-Weon Kim
发明人： Young Ju Kim , Kwan-Weon Kim
IPC分类号： H05K1/02 , H03K19/0175
CPC分类号： H03K19/0016
摘要： A semiconductor integrated circuit includes a first clock pin controller that receives a mirror function signal and a test mode signal to generate a first input buffer control signal in response to the mirror function signal in a normal mode. A second clock pin controller receives the mirror function signal and the test mode signal to generate a second input buffer control signal, which is an inverted signal of the first input buffer control signal, in response to the mirror function signal in the normal mode. An input buffer unit generates output signals of first and second pins in response to the first input buffer control signal and the second input buffer control signal, respectively.
摘要翻译：半导体集成电路包括：第一时钟引脚控制器，其接收反射镜功能信号和测试模式信号，以响应正常模式下的镜像功能信号产生第一输入缓冲器控制信号。第二时钟引脚控制器响应于正常模式下的镜像功能信号，接收镜像功能信号和测试模式信号，以产生作为第一输入缓冲器控制信号的反相信号的第二输入缓冲器控制信号。输入缓冲单元分别响应于第一输入缓冲器控制信号和第二输入缓冲器控制信号产生第一和第二引脚的输出信号。

3. 发明申请

US20120217654A1 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120217654A1
公开(公告)日：2012-08-30
申请号：US13292609
申请日：2011-11-09
申请人： Sang-Hoon SHIN , Kwan-Weon Kim
发明人： Sang-Hoon SHIN , Kwan-Weon Kim
IPC分类号： H01L27/10 , H01L21/78 , H01L21/50
CPC分类号： H01L22/20 , G11C5/04 , G11C29/08 , H01L21/561 , H01L22/14 , H01L24/94 , H01L24/97 , H01L25/50 , H01L2224/16145 , H01L2224/94 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06593 , H01L2225/06596 , H01L2224/81
摘要： A semiconductor device includes a wafer comprising a chip that passes a test and a chip that does not pass a test, one or more first stacked chips that are stacked over the chip that passes a test, and one or more second stacked chips that are stacked over the chip that does not pass a test, wherein the second stacked chips comprise at least one between an chip that does not pass a test and a dummy chip.
摘要翻译：半导体器件包括：晶片，其包括通过测试的芯片和不通过测试的芯片，堆叠在通过测试的芯片上的一个或多个第一堆叠芯片和堆叠的一个或多个第二堆叠芯片在芯片上不通过测试，其中第二堆叠芯片包括不通过测试的芯片和虚设芯片之间的至少一个芯片。

4. 发明授权

US06717884B2 Synchronous memory device with reduced address pins 有权
标题翻译：具有减少地址引脚的同步存储器件
公开(公告)号：US06717884B2
公开(公告)日：2004-04-06
申请号：US10198926
申请日：2002-07-22
申请人： Kwan-Weon Kim
发明人： Kwan-Weon Kim
IPC分类号： G11C800
CPC分类号： G11C7/1087 , G11C5/066 , G11C7/1072 , G11C7/1078 , G11C11/4082 , G11C2207/107
摘要： A synchronous memory device is capable of reducing the number of address pins by changing address input. The synchronous memory device includes at least one common pin receiving a first signal and a second signal, latch circuits coupled to the common pin, wherein the latch circuit latches the first and second signals and one of the latch circuits selectively outputs the first or second signal in response to first or second internal clock pulses, and a clock pulse generator for receiving an external clock signal and for producing the first and second internal clock pulses from the external clock signal.
摘要翻译：同步存储器件能够通过改变地址输入来减少地址引脚的数量。同步存储器件包括至少一个公共引脚，接收第一信号和第二信号，锁存电路耦合到公共引脚，其中锁存电路锁存第一和第二信号，其中一个锁存电路有选择地输出第一或第二信号响应于第一或第二内部时钟脉冲，以及时钟脉冲发生器，用于接收外部时钟信号，并用于从外部时钟信号产生第一和第二内部时钟脉冲。

5. 发明授权

US08120416B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US08120416B2
公开(公告)日：2012-02-21
申请号：US12166085
申请日：2008-07-01
申请人： Kwan-Weon Kim , Jun-Ho Lee , Kun-Woo Park , Chang-Kyu Choi , Yong-Ju Kim , Sung-Woo Han , Jun-Woo Lee
发明人： Kwan-Weon Kim , Jun-Ho Lee , Kun-Woo Park , Chang-Kyu Choi , Yong-Ju Kim , Sung-Woo Han , Jun-Woo Lee
IPC分类号： H04B1/10
CPC分类号： H03K19/00369
摘要： A semiconductor integrated circuit can include a first voltage pad, a second voltage pad, and a voltage stabilizing unit that is connected between the first voltage pad and the second voltage pad. The first voltage pad can be connected to a first internal circuit, and the second voltage pad can be connected to a second internal circuit.
摘要翻译：半导体集成电路可以包括连接在第一电压焊盘和第二电压焊盘之间的第一电压焊盘，第二电压焊盘和稳压单元。第一电压焊盘可以连接到第一内部电路，并且第二电压焊盘可以连接到第二内部电路。

6. 发明申请

US20080074139A1 Semiconductor memory device with on-die termination circuit 有权
标题翻译：具有片上终端电路的半导体存储器件
公开(公告)号：US20080074139A1
公开(公告)日：2008-03-27
申请号：US11819800
申请日：2007-06-29
申请人： Kwan-Weon Kim , Jeong-Woo Lee
发明人： Kwan-Weon Kim , Jeong-Woo Lee
IPC分类号： H03K19/003 , H03K5/22
CPC分类号： H04L25/0278 , H03K19/017545 , H03K19/017581 , H04L25/028
摘要： A semiconductor memory device is able to inactivate an on-die termination circuit without an additional pin. The semiconductor memory device includes a control signal generator, a resistance control unit, and a resistance supply unit. The control signal generator generates an initializing signal and driving clocks in response to a plurality of control signals. The resistance control unit, initialized by the initializing signal, generates a termination-off signal in response to the driving clocks. The resistance supply unit supplies termination resistance in response to the termination-off signal and a mode register setting value. The plurality of control signals are inputted through input pins not connected to the resistance supply unit.
摘要翻译：半导体存储器件能够在没有附加引脚的情况下使管芯端接电路失活。半导体存储器件包括控制信号发生器，电阻控制单元和电阻供应单元。控制信号发生器响应于多个控制信号产生初始化信号和驱动时钟。由初始化信号初始化的电阻控制单元响应于驱动时钟产生终止关闭信号。电阻供应单元响应于终止信号和模式寄存器设置值提供终止电阻。多个控制信号通过未连接到电阻供应单元的输入引脚输入。

7. 发明授权

US07042774B2 Semiconductor memory device to supply stable high voltage during auto-refresh operation and method therefor 有权
标题翻译：在自动刷新操作期间提供稳定的高电压的半导体存储器件及其方法
公开(公告)号：US07042774B2
公开(公告)日：2006-05-09
申请号：US10881434
申请日：2004-06-29
申请人： Kwan-Weon Kim
发明人： Kwan-Weon Kim
IPC分类号： G11C7/00
CPC分类号： G11C11/40611 , G11C11/406 , G11C11/4074
摘要： A semiconductor device for use in a semiconductor memory device for pumping a supplying voltage according to a data access mode and an auto-refresh mode, including: a voltage level detecting means for generating a voltage level detect signal by detecting a voltage level of the supplying voltage; an auto-refresh signal detecting means for generating an auto-refresh detect signal in response to an auto-refresh signal; and a voltage pumping means for pumping the supplying voltage in response to the voltage level detect signal at the data access mode or in response to the auto-refresh detect signal at the auto-refresh mode.
摘要翻译：一种用于半导体存储器件的半导体器件，用于根据数据存取模式和自动刷新模式对供电电压进行泵浦，包括：电压电平检测装置，用于通过检测供电电压的电压电平来产生电压电平检测信号电压; 自动刷新信号检测装置，用于响应于自动刷新信号产生自动刷新检测信号; 以及用于在数据访问模式下响应于电压电平检测信号或响应于自动刷新模式下的自动刷新检测信号来泵送供电电压的电压泵送装置。

8. 发明授权

US06657908B2 DDR SDRAM for stable read operation 失效
公开(公告)号：US06657908B2
公开(公告)日：2003-12-02
申请号：US10283535
申请日：2002-10-29
申请人： Young-Jin Yoon , Kwan-Weon Kim
发明人： Young-Jin Yoon , Kwan-Weon Kim
IPC分类号： G11C1300
CPC分类号： G11C7/1066 , G11C7/1048 , G11C11/4076 , G11C11/4096
摘要： A synchronous memory device which comprises global I/O lines for data input and output from and to a memory core and a pipeline latch circuit for latching data from the global I/O lines. The synchronous memory device includes a circuit that precharges the global I/O lines when a read command signal interrupts a write operation signal, and disables the pipeline latch circuit in order to prevent write data on the global I/O lines from being latched in the pipeline latch circuit. Accordingly, the write data is prevented from being transferred to the pipeline latch circuit at an early stage of the read operation.

9. 发明授权

US07924647B2 Fuse circuit and driving method thereof 有权
标题翻译：保险丝电路及其驱动方法
公开(公告)号：US07924647B2
公开(公告)日：2011-04-12
申请号：US12494616
申请日：2009-06-30
申请人： Keun-Soo Song , Kwan-Weon Kim
发明人： Keun-Soo Song , Kwan-Weon Kim
IPC分类号： G11C17/18
CPC分类号： G11C29/785 , G11C17/18 , G11C29/02 , G11C29/027
摘要： A fuse circuit includes a fuse unit configured to form a current path on a first node according to whether or not a fuse is cut; a driving current controller configured to control a potential level of the first node in response to a test signal; and an output unit configured to output a fuse state signal in response to the potential level of the first node.
摘要翻译：保险丝电路包括：熔丝单元，被配置为根据是否切断熔丝形成第一节点上的电流路径; 驱动电流控制器，被配置为响应于测试信号来控制所述第一节点的电位电平; 以及输出单元，被配置为响应于第一节点的电位电平输出熔丝状态信号。

10. 发明授权

US07589654B2 Digital-to-analog converting circuit and apparatus for on-die termination using the same 有权
标题翻译：数模转换电路及使用其的片上终端装置
公开(公告)号：US07589654B2
公开(公告)日：2009-09-15
申请号：US12026465
申请日：2008-02-05
申请人： Kwan-Weon Kim
发明人： Kwan-Weon Kim
IPC分类号： H03M1/66
CPC分类号： G11C7/1051 , G11C7/1057 , H03M1/1057 , H03M1/808 , H04L25/0278
摘要： A digital-to-analogue converting circuit includes a driver leg having a plurality of resistance elements between a power supply voltage terminal and a ground voltage terminal, wherein at least one of the plurality of resistance elements is a variable resistor, and a code level changing unit for outputting a level-changed code to a control terminal of the variable resistor based on an activation of a digital code, wherein the level-changed code is produced by converting a level of the digital code.
摘要翻译：数模转换电路包括在电源电压端和地电压端之间具有多个电阻元件的驱动器支脚，其中多个电阻元件中的至少一个是可变电阻器，并且代码电平变化单元，用于基于数字代码的激活将电平变化的代码输出到可变电阻器的控制端子，其中通过转换数字代码的电平来产生电平变化的代码。

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