专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08578227B2 Delay test device and system-on-chip having the same 有权
标题翻译：延迟测试设备和片上系统具有相同的功能
公开(公告)号：US08578227B2
公开(公告)日：2013-11-05
申请号：US12944787
申请日：2010-11-12
申请人： Young-Jae Son , Yong-Jin Yoon , Uk-Rae Cho
发明人： Young-Jae Son , Yong-Jin Yoon , Uk-Rae Cho
IPC分类号： G01R31/28
CPC分类号： G01R31/31725 , G06F11/24
摘要： A test device for a system-on-chip includes a sequential logic circuit and a test circuit. The sequential logic circuit generates a test input signal by converting a serial input signal into a parallel format in response to a serial clock signal and a serial enable signal and generates a serial output signal by converting a test output signal into a serial format in response to the serial clock signal and the serial enable signal. The test circuit includes at least one delay unit that is separated from a logic circuit performing original functions of the system-on-chip, performs a delay test on the at least one delay unit using the test input signal in response to a system clock signal and a test enable signal, and provides the test output signal to the sequential logic circuit, where the test output signal representing a result of the delay test.
摘要翻译：用于片上系统的测试装置包括顺序逻辑电路和测试电路。顺序逻辑电路通过根据串行时钟信号和串行使能信号将串行输入信号转换为并行格式产生测试输入信号，并通过将测试输出信号转换成串行格式来响应于串行时钟信号和串行使能信号。测试电路包括至少一个延迟单元，其与执行片上系统的原始功能的逻辑电路分离，响应于系统时钟信号，使用测试输入信号对至少一个延迟单元执行延迟测试和测试使能信号，并将测试输出信号提供给顺序逻辑电路，其中测试输出信号表示延迟测试的结果。

2. 发明授权

US06901014B2 Circuits and methods for screening for defective memory cells in semiconductor memory devices 失效
标题翻译：用于筛选半导体存储器件中的有缺陷的存储单元的电路和方法
公开(公告)号：US06901014B2
公开(公告)日：2005-05-31
申请号：US10445468
申请日：2003-05-27
申请人： Young-Jae Son , Uk-Rae Cho , Kwang-Jin Lee
发明人： Young-Jae Son , Uk-Rae Cho , Kwang-Jin Lee
IPC分类号： G01R31/28 , G11C11/413 , G11C29/00 , G11C29/06 , G11C29/50
CPC分类号： G11C29/12005 , G11C11/41 , G11C29/50 , G11C2029/5002 , G11C2029/5006
摘要： Circuits and methods that enable screening for defective or weak memory cells in a semiconductor memory device. In one aspect, a semiconductor memory device comprises first and second drivers for a SRAM cell. The first driver is connected between a power supply voltage and the cell, which supplies the power supply voltage into the cell in response to a cell power control signal. The second driver is connected between the power supply signal and the cell, which supplies a voltage lower than the power supply voltage into the cell in response to the cell power down signal. A method for screening for defective or weak cells does not require a time for stabilizing a circuit condition after voltage variation to supply the voltage lower than the power supply voltage from a conventional tester because the cell power down signal activates a driver that causes a supply voltage that is lower than the power supply voltage to be loaded directly to the cell, which results in a reduction of the test time for screening defective cells.
摘要翻译：能够筛选半导体存储器件中的缺陷或弱存储器单元的电路和方法。在一个方面，半导体存储器件包括用于SRAM单元的第一和第二驱动器。第一驱动器连接在电源电压和电池之间，其响应于电池功率控制信号将电源电压提供给电池。第二驱动器连接在电源信号和单元之间，其响应于单元断电信号而向电池提供低于电源电压的电压。用于筛选有缺陷或弱电池的方法不需要时间来稳定电压变化之后的电路状况，以从常规测试器提供低于电源电压的电压，因为电池停电信号激活导致电源电压的驱动器低于要直接加载到电池的电源电压，这样可以减少用于筛选有缺陷的电池的测试时间。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式