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    • 1. 发明授权
    • Electrode tool for electrochemical machining and method of manufacturing the same
    • 用于电化学加工的电极工具及其制造方法
    • US08317995B2
    • 2012-11-27
    • US12285878
    • 2008-10-15
    • Young Tae KimYoung Hwan LimIl Oung ParkWon Seok ChoiJong Yun Kim
    • Young Tae KimYoung Hwan LimIl Oung ParkWon Seok ChoiJong Yun Kim
    • B23H7/22
    • B23H9/00B23H5/06B23H2200/10
    • Disclosed herein is a highly-durable electrode tool for electrochemical machining, which can prevent the corrosion and abrasion of a conductive pattern at the time of electrochemical machining for forming dynamic pressure-generating grooves of a fluid dynamic bearing, and a method of manufacturing the same. The electrode tool for electrochemical machining includes: an electrode substrate on which a conductive pattern is formed to have protrusions corresponding to the fine grooves and to which negative current is applied; a nonconductive insulating layer, covering an entire top surface of the electrode substrate excluding the conductive pattern; and a conductive layer, which is formed on the conductive pattern to protect the conductive pattern, and a top surface of which is the same height as a top surface of the nonconductive insulating layer.
    • 本发明公开了一种用于电化学加工的高耐用性电极工具,其可以防止在用于形成流体动力轴承的动态压力产生槽的电化学加工时的导电图案的腐蚀和磨损及其制造方法 。 用于电化学加工的电极工具包括:电极基板,其上形成导电图案以具有对应于细槽的突起并施加负电流; 绝缘绝缘层,覆盖除了导电图案之外的电极基板的整个顶表面; 以及导电层,其形成在导电图案上以保护导电图案,并且其顶表面与非导电绝缘层的顶表面具有相同的高度。
    • 9. 发明授权
    • Semiconductor memory device and data read method thereof
    • 半导体存储器件及其数据读取方法
    • US06295244B1
    • 2001-09-25
    • US09617524
    • 2000-07-17
    • Young Tae KimDeok Joon Shin
    • Young Tae KimDeok Joon Shin
    • G11C800
    • G11C7/1057G11C7/1051G11C7/106G11C7/1069G11C2207/2281
    • The present invention discloses a semiconductor memory device. The device includes a plurality of memory cell array blocks; a predetermined number of main buffers for resetting a predetermined number of pairs of main data lines corresponding to a predetermined number of pairs of data items output from each of the plurality of memory cell array blocks in response to a main buffer control signal, and for generating a predetermined number of pairs of data when the data of each of the predetermined number of pairs of main data lines become complementary levels, the predetermined number of pair of data being reset after a lapse of predetermined time; a predetermined number of data output buffers for respectively receiving and buffering the predetermined number of pairs of data items generated by the predetermined number of main buffers, in response to a data output buffer control signal; and data output buffer control signal generating means for generating the data output buffer control signal, the data output buffer control signal being enabled in response to a control signal and disabled after a lapse of predetermined time from the point of time at which each of the pair of data items output from the predetermined number of main buffers reaches the desired complementary levels, thereby improving data read speed.
    • 本发明公开了一种半导体存储器件。 该装置包括多个存储单元阵列块; 预定数量的主缓冲器,用于响应于主缓冲器控制信号来复位与从多个存储单元阵列块中的每一个输出的预定数量的数据对对应的预定数量的主数据线对,并且用于生成 当预定数量的主数据线对中的每一个的数据成为互补电平时,预定数量的数据对,预定数量的数据对在经过预定时间之后被复位; 预定数量的数据输出缓冲器,用于响应于数据输出缓冲器控制信号分别接收和缓冲由预定数量的主缓冲器产生的预定数量的数据项对; 以及数据输出缓冲器控制信号产生装置,用于产生数据输出缓冲器控制信号,数据输出缓冲器控制信号响应于控制信号被使能,并且在从该对中的每一个的时间点起经过预定​​时间后被禁用 从预定数量的主缓冲器输出的数据项达到期望的互补电平,从而提高数据读取速度。