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    • 5. 发明申请
    • Porous hydrodynamic bearing
    • 多孔流体动力轴承
    • US20120014629A1
    • 2012-01-19
    • US13137026
    • 2011-07-15
    • Young Tae KimTa Kyoung Lee
    • Young Tae KimTa Kyoung Lee
    • F16C32/06B23H3/00
    • F16C33/103
    • There is provided a porous hydrodynamic bearing including a sleeve supporting a shaft, wherein the sleeve is formed of a sintered body containing at least one metal powder selected from a group consisting of SUS 304, SUS 430, and iron (Fe). In the sleeve formed of the sintered body containing at least one metal powder selected from the group consisting of SUS 304, SUS 430, and iron (Fe), surface pores and inner pores are not in communication with each other, whereby a leakage phenomenon of dynamic pressure may be reduced, as compared to a sleeve made of an alloy of Cu and Fe in which opened pores are formed.
    • 提供了一种多孔流体动力轴承,其包括支撑轴的套筒,其中套筒由包含至少一种选自SUS 304,SUS 430和铁(Fe)的金属粉末的烧结体形成。 在由含有选自SUS304,SUS330和铁(Fe)中的至少一种金属粉末的烧结体形成的套筒中,表面孔和内孔彼此不连通,由此产生泄漏现象 与由形成开放孔的Cu和Fe的合金制成的套管相比,可以减小动态压力。
    • 9. 发明授权
    • Semiconductor memory device and data read method thereof
    • 半导体存储器件及其数据读取方法
    • US06295244B1
    • 2001-09-25
    • US09617524
    • 2000-07-17
    • Young Tae KimDeok Joon Shin
    • Young Tae KimDeok Joon Shin
    • G11C800
    • G11C7/1057G11C7/1051G11C7/106G11C7/1069G11C2207/2281
    • The present invention discloses a semiconductor memory device. The device includes a plurality of memory cell array blocks; a predetermined number of main buffers for resetting a predetermined number of pairs of main data lines corresponding to a predetermined number of pairs of data items output from each of the plurality of memory cell array blocks in response to a main buffer control signal, and for generating a predetermined number of pairs of data when the data of each of the predetermined number of pairs of main data lines become complementary levels, the predetermined number of pair of data being reset after a lapse of predetermined time; a predetermined number of data output buffers for respectively receiving and buffering the predetermined number of pairs of data items generated by the predetermined number of main buffers, in response to a data output buffer control signal; and data output buffer control signal generating means for generating the data output buffer control signal, the data output buffer control signal being enabled in response to a control signal and disabled after a lapse of predetermined time from the point of time at which each of the pair of data items output from the predetermined number of main buffers reaches the desired complementary levels, thereby improving data read speed.
    • 本发明公开了一种半导体存储器件。 该装置包括多个存储单元阵列块; 预定数量的主缓冲器,用于响应于主缓冲器控制信号来复位与从多个存储单元阵列块中的每一个输出的预定数量的数据对对应的预定数量的主数据线对,并且用于生成 当预定数量的主数据线对中的每一个的数据成为互补电平时,预定数量的数据对,预定数量的数据对在经过预定时间之后被复位; 预定数量的数据输出缓冲器,用于响应于数据输出缓冲器控制信号分别接收和缓冲由预定数量的主缓冲器产生的预定数量的数据项对; 以及数据输出缓冲器控制信号产生装置,用于产生数据输出缓冲器控制信号,数据输出缓冲器控制信号响应于控制信号被使能,并且在从该对中的每一个的时间点起经过预定​​时间后被禁用 从预定数量的主缓冲器输出的数据项达到期望的互补电平,从而提高数据读取速度。