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1. 发明授权

US08836027B2 Switch circuit using LDMOS element 有权
标题翻译：开关电路采用LDMOS元件
公开(公告)号：US08836027B2
公开(公告)日：2014-09-16
申请号：US13425357
申请日：2012-03-20
申请人： Young Jin Woo , Kong Soon Park , Young Sik Kim
发明人： Young Jin Woo , Kong Soon Park , Young Sik Kim
IPC分类号： H01L27/06 , H03K17/10 , H03K17/687 , H01L29/78 , H01L29/10
CPC分类号： H03K17/102 , H01L29/1083 , H01L29/7835 , H03K17/6874
摘要： The present invention relates to a switch circuit, and more particularly, to a switch circuit that uses an LDMOS (lateral diffusion metal oxide semiconductor) device inside an IC (Integrated Circuit). In the switch circuit that uses the LDMOS device according to an embodiment of the present invention, a gate-source voltage (VGS) of the LDMOS device may be stably controlled through a current source and resistances, the characteristics of a switch may be maintained regardless of the voltages of both terminals (A and B) by using an N-type LDMOS and a P-type LDMOS in a complementary manner, and the current generated by the current source is offset inside the switch without flowing to the outside of the switch.
摘要翻译：开关电路技术领域本发明涉及开关电路，更具体地说，涉及在IC（集成电路）内使用LDMOS（横向扩散金属氧化物半导体）器件的开关电路。在使用根据本发明的实施例的LDMOS器件的开关电路中，可以通过电流源和电阻稳定地控制LDMOS器件的栅极 - 源极电压（VGS），开关的特性可以保持不变通过以互补的方式使用N型LDMOS和P型LDMOS来实现两端（A和B）的电压，并且由电流源产生的电流在开关内部偏移而不流到开关的外部。

2. 发明授权

US08183089B2 Method for manufacturing package system incorporating flip-chip assembly 有权
标题翻译：用于制造包括倒装芯片组装的封装系统的方法
公开(公告)号：US08183089B2
公开(公告)日：2012-05-22
申请号：US12976753
申请日：2010-12-22
申请人： A Leam Choi , Young Jin Woo , Junwoo Myung
发明人： A Leam Choi , Young Jin Woo , Junwoo Myung
IPC分类号： H01L21/44
CPC分类号： H01L23/3135 , H01L21/563 , H01L21/565 , H01L23/13 , H01L23/3128 , H01L23/49827 , H01L23/5385 , H01L24/73 , H01L25/03 , H01L25/105 , H01L2224/05571 , H01L2224/05573 , H01L2224/16145 , H01L2224/16225 , H01L2224/1703 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73203 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2225/06558 , H01L2225/1023 , H01L2225/1058 , H01L2225/1088 , H01L2924/00014 , H01L2924/14 , H01L2924/15151 , H01L2924/15311 , H01L2924/1815 , H01L2924/19107 , H01L2924/3025 , H01L2924/00012 , H01L2924/00 , H01L2224/05599
摘要： A method for manufacturing a package system includes: providing a first semiconductor die; mounting a second semiconductor die on the first semiconductor die using an inter-die interconnect to form a flip-chip assembly; and attaching the flip-chip assembly on a package substrate with a contact pad, a test connection, a z-bond pad, and a die receptacle, with the first semiconductor die in the flip-chip assembly fitting inside the die receptacle.
摘要翻译：一种制造封装系统的方法，包括：提供第一半导体管芯; 使用晶片间互连来将第二半导体管芯安装在第一半导体管芯上以形成倒装芯片组件; 以及将所述倒装芯片组件安装在具有接触焊盘，测试连接件，z焊盘和模具插座的封装衬底上，所述倒装芯片组件中的所述第一半导体管芯装配在所述管芯插座内。

3. 发明申请

US20120032340A1 Semiconductor Die and Method of Forming FO-WLCSP Vertical Interconnect Using TSV and TMV 有权
标题翻译：半导体芯片和使用TSV和TMV形成FO-WLCSP垂直互连的方法
公开(公告)号：US20120032340A1
公开(公告)日：2012-02-09
申请号：US12852433
申请日：2010-08-06
申请人： DaeSik Choi , Young Jin Woo , TaeWoo Lee
发明人： DaeSik Choi , Young Jin Woo , TaeWoo Lee
IPC分类号： H01L23/48 , H01L21/50 , H01L21/56
CPC分类号： H01L21/78 , H01L21/561 , H01L21/568 , H01L23/147 , H01L23/3114 , H01L23/3128 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L24/16 , H01L24/17 , H01L24/24 , H01L24/29 , H01L24/48 , H01L24/73 , H01L24/82 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L2224/0401 , H01L2224/04105 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2224/24146 , H01L2224/24225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73253 , H01L2224/73265 , H01L2224/73267 , H01L2224/8203 , H01L2224/92 , H01L2224/92244 , H01L2224/97 , H01L2225/06517 , H01L2225/06541 , H01L2225/06548 , H01L2225/06572 , H01L2225/1023 , H01L2225/1035 , H01L2225/1058 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01047 , H01L2924/01049 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/078 , H01L2924/09701 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/351 , H01L2224/82 , H01L2224/83 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device has a TSV wafer and semiconductor die mounted over the TSV wafer. A channel is formed through the TSV wafer. An encapsulant is deposited over the semiconductor die and TSV wafer. Conductive TMV are formed through the encapsulant over the conductive TSV and contact pads of the semiconductor die. The conductive TMV can be formed through the channel. A conductive layer is formed over the encapsulant and electrically connected to the conductive TMV. The conductive TMV are formed during the same manufacturing process. An insulating layer is formed over the encapsulant and conductive layer. A plurality of semiconductor die of the same size or different sizes can be stacked over the TSV wafer. The plurality of semiconductor die can be stacked over opposite sides of the TSV wafer. An internal stacking module can be stacked over the semiconductor die and electrically connected through the conductive TMV.
摘要翻译：半导体器件具有安装在TSV晶片上的TSV晶片和半导体管芯。通过TSV晶片形成通道。密封剂沉积在半导体管芯和TSV晶片上。导电TMV通过半导体芯片的导电TSV和接触焊盘上的密封剂形成。可以通过通道形成导电TMV。导电层形成在密封剂上方并与导电TMV电连接。导电TMV在相同的制造过程中形成。绝缘层形成在密封剂和导电层之上。可以在TSV晶片上堆叠相同尺寸或不同尺寸的多个半导体管芯。多个半导体管芯可以堆叠在TSV晶片的相对侧上。内部堆叠模块可以堆叠在半导体裸片上并通过导电TMV电连接。

4. 发明申请

US20110092021A1 METHOD FOR MANUFACTURING PACKAGE SYSTEM INCORPORATING FLIP-CHIP ASSEMBLY 有权
标题翻译：制造卷芯片组装的包装系统的方法
公开(公告)号：US20110092021A1
公开(公告)日：2011-04-21
申请号：US12976753
申请日：2010-12-22
申请人： A Leam Choi , Young Jin Woo , Junwoo Myung
发明人： A Leam Choi , Young Jin Woo , Junwoo Myung
IPC分类号： H01L21/50
CPC分类号： H01L23/3135 , H01L21/563 , H01L21/565 , H01L23/13 , H01L23/3128 , H01L23/49827 , H01L23/5385 , H01L24/73 , H01L25/03 , H01L25/105 , H01L2224/05571 , H01L2224/05573 , H01L2224/16145 , H01L2224/16225 , H01L2224/1703 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73203 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2225/06558 , H01L2225/1023 , H01L2225/1058 , H01L2225/1088 , H01L2924/00014 , H01L2924/14 , H01L2924/15151 , H01L2924/15311 , H01L2924/1815 , H01L2924/19107 , H01L2924/3025 , H01L2924/00012 , H01L2924/00 , H01L2224/05599
摘要： A method for manufacturing a package system includes: providing a first semiconductor die; mounting a second semiconductor die on the first semiconductor die using an inter-die interconnect to form a flip-chip assembly; and attaching the flip-chip assembly on a package substrate with a contact pad, a test connection, a z-bond pad, and a die receptacle, with the first semiconductor die in the flip-chip assembly fitting inside the die receptacle.
摘要翻译：一种制造封装系统的方法，包括：提供第一半导体管芯; 使用晶片间互连来将第二半导体管芯安装在第一半导体管芯上以形成倒装芯片组件; 以及将所述倒装芯片组件安装在具有接触焊盘，测试连接件，z焊盘和模具插座的封装衬底上，所述倒装芯片组件中的所述第一半导体管芯装配在所述管芯插座内。

5. 发明申请

US20090283888A1 PACKAGE SYSTEM INCORPORATING A FLIP-CHIP ASSEMBLY 有权
标题翻译：包装卷烟组件的包装系统
公开(公告)号：US20090283888A1
公开(公告)日：2009-11-19
申请号：US12122631
申请日：2008-05-16
申请人： A Leam Choi , Young Jin Woo , Junwoo Myung
发明人： A Leam Choi , Young Jin Woo , Junwoo Myung
IPC分类号： H01L23/538 , H01L21/56
CPC分类号： H01L23/3135 , H01L21/563 , H01L21/565 , H01L23/13 , H01L23/3128 , H01L23/49827 , H01L23/5385 , H01L24/73 , H01L25/03 , H01L25/105 , H01L2224/05571 , H01L2224/05573 , H01L2224/16145 , H01L2224/16225 , H01L2224/1703 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73203 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2225/06558 , H01L2225/1023 , H01L2225/1058 , H01L2225/1088 , H01L2924/00014 , H01L2924/14 , H01L2924/15151 , H01L2924/15311 , H01L2924/1815 , H01L2924/19107 , H01L2924/3025 , H01L2924/00012 , H01L2924/00 , H01L2224/05599
摘要： A package system including providing a first semiconductor die; mounting a second semiconductor die on the first semiconductor die using an inter-die interconnect to form a flip-chip assembly; and attaching the flip-chip assembly on a package substrate with a contact pad, a test connection, a z-bond pad, and a die receptacle, with the first semiconductor die in the flip-chip assembly fitting inside the die receptacle.
摘要翻译：一种包装系统，包括提供第一半导体管芯; 使用晶片间互连来将第二半导体管芯安装在第一半导体管芯上以形成倒装芯片组件; 以及将所述倒装芯片组件安装在具有接触焊盘，测试连接件，z焊盘和模具插座的封装衬底上，所述倒装芯片组件中的所述第一半导体管芯装配在所述管芯插座内。

6. 发明授权

US08895440B2 Semiconductor die and method of forming Fo-WLCSP vertical interconnect using TSV and TMV 有权
标题翻译：半导体芯片和使用TSV和TMV形成Fo-WLCSP垂直互连的方法
公开(公告)号：US08895440B2
公开(公告)日：2014-11-25
申请号：US12852433
申请日：2010-08-06
申请人： DaeSik Choi , Young Jin Woo , TaeWoo Lee
发明人： DaeSik Choi , Young Jin Woo , TaeWoo Lee
IPC分类号： H01L21/56 , H01L21/768 , H01L23/00 , H01L21/78 , H01L23/498 , H01L23/31 , H01L23/14 , H01L25/10
CPC分类号： H01L21/78 , H01L21/561 , H01L21/568 , H01L23/147 , H01L23/3114 , H01L23/3128 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L24/16 , H01L24/17 , H01L24/24 , H01L24/29 , H01L24/48 , H01L24/73 , H01L24/82 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L2224/0401 , H01L2224/04105 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2224/24146 , H01L2224/24225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73253 , H01L2224/73265 , H01L2224/73267 , H01L2224/8203 , H01L2224/92 , H01L2224/92244 , H01L2224/97 , H01L2225/06517 , H01L2225/06541 , H01L2225/06548 , H01L2225/06572 , H01L2225/1023 , H01L2225/1035 , H01L2225/1058 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01047 , H01L2924/01049 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/078 , H01L2924/09701 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/351 , H01L2224/82 , H01L2224/83 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device has a TSV wafer and semiconductor die mounted over the TSV wafer. A channel is formed through the TSV wafer. An encapsulant is deposited over the semiconductor die and TSV wafer. Conductive TMV are formed through the encapsulant over the conductive TSV and contact pads of the semiconductor die. The conductive TMV can be formed through the channel. A conductive layer is formed over the encapsulant and electrically connected to the conductive TMV. The conductive TMV are formed during the same manufacturing process. An insulating layer is formed over the encapsulant and conductive layer. A plurality of semiconductor die of the same size or different sizes can be stacked over the TSV wafer. The plurality of semiconductor die can be stacked over opposite sides of the TSV wafer. An internal stacking module can be stacked over the semiconductor die and electrically connected through the conductive TMV.
摘要翻译：半导体器件具有安装在TSV晶片上的TSV晶片和半导体管芯。通过TSV晶片形成通道。密封剂沉积在半导体管芯和TSV晶片上。导电TMV通过半导体芯片的导电TSV和接触焊盘上的密封剂形成。可以通过通道形成导电TMV。导电层形成在密封剂上方并与导电TMV电连接。导电TMV在相同的制造过程中形成。绝缘层形成在密封剂和导电层之上。可以在TSV晶片上堆叠相同尺寸或不同尺寸的多个半导体管芯。多个半导体管芯可以堆叠在TSV晶片的相对侧上。内部堆叠模块可以堆叠在半导体裸片上并通过导电TMV电连接。

7. 发明授权

US08576635B2 Nonvolatile memory device and method of operating the same 有权
标题翻译：非易失存储器件及其操作方法
公开(公告)号：US08576635B2
公开(公告)日：2013-11-05
申请号：US13176156
申请日：2011-07-05
申请人： Nam Kyeong Kim , Kyoung Chul Yang , Young Jin Woo , Tae Hyun Kim
发明人： Nam Kyeong Kim , Kyoung Chul Yang , Young Jin Woo , Tae Hyun Kim
IPC分类号： G11C16/04
CPC分类号： G11C16/16 , G11C16/0483
摘要： A nonvolatile memory device includes memory cell blocks each configured to comprise memory cells erased by an erase voltage, supplied to a word line, and a bulk voltage supplied to a bulk, a bias voltage generator configured to generate a first erase voltage, having a first pulse width and a first amplitude, in order to perform the erase operation of the memory cells and a second erase voltage, having a second pulse width narrower than the first pulse width and a second amplitude lower than the first amplitude, in order to perform an additional erase operation if an unerased memory cell is detected after the erase operation is performed, and a bulk voltage generator configured to generate the bulk voltage.
摘要翻译：非易失性存储器件包括存储单元块，每个存储单元块被配置为包括被提供给字线的擦除电压擦除的存储器单元和提供给块的体电压;偏置电压发生器，被配置为产生第一擦除电压，脉冲宽度和第一幅度，以便执行具有比第一脉冲宽度窄的第二脉冲宽度和低于第一幅度的第二幅度的存储单元的擦除操作和第二擦除电压，以便执行在执行擦除操作之后检测到未故障存储器单元的附加擦除操作，以及被配置为产生体电压的体电压发生器。

8. 发明授权

US06437360B1 Vacuum field transistor 失效
标题翻译：真空场晶体管
公开(公告)号：US06437360B1
公开(公告)日：2002-08-20
申请号：US09647076
申请日：2000-11-09
申请人： Gyu Hyeong Cho , Ji Yeoul Ryoo , Myeoung Wun Hwang , Min Hyung Cho , Young Jin Woo , Young Ki Kim
发明人： Gyu Hyeong Cho , Ji Yeoul Ryoo , Myeoung Wun Hwang , Min Hyung Cho , Young Jin Woo , Young Ki Kim
IPC分类号： H01L2906
CPC分类号： H01J1/316 , H01J21/105
摘要： Disclosed are flat/vertical type vacuum field transistor (VFT) structures, which adopt a MOSFET-like flat or vertical structure so as to increase the degree of integration and can be operated at low operation voltages at high speeds. The flat type comprises a source and a drain, made of conductors, which stand at a predetermined distance apart on a thin channel insulator with a vacuum channel therebetween; a gate, made of a conductor, which is formed with a width below the source and the drain, the channel insulator functioning to insulate the gate from the source and the drain; and an insulating body, which serves as a base for propping up the channel insulator and the gate. The vertical type comprises a conductive, continuous circumferential source with a void center, formed on a channel insulator; a conductive gate formed below the channel insulator, extending across the source; an insulating body for serving as a base to support the gate and the channel insulator; an insulating walls which stand over the source, forming a closed vacuum channel; and a drain formed over the vacuum channel. In both types, proper bias voltages are applied among the gate, the source and the drain to enable electrons to be field emitted from the source through the vacuum channel to the drain.
摘要翻译：公开了平面/垂直型真空场效应晶体管（VFT）结构，它们采用类似MOSFET的平面或垂直结构，以增加集成度，并可在高速下在低工作电压下工作。扁平型包括由导体制成的源极和漏极，它们在薄沟道绝缘体上以预定的距离隔开，其间具有真空通道; 由导体制成的栅极，其形成在源极和漏极下方的宽度，沟道绝缘体用于使栅极与源极和漏极绝缘; 以及用作支撑通道绝缘体和栅极的基座的绝缘体。垂直型包括形成在通道绝缘体上的具有空心中心的导电连续周向源; 导电栅极，形成在沟道绝缘体下方，延伸穿过源极; 用作支撑栅极和沟道绝缘体的基座的绝缘体; 绝缘壁，其竖立在源上，形成封闭的真空通道; 以及在真空通道上形成的排水口。在这两种类型中，在栅极，源极和漏极之间施加适当的偏置电压，以使电子能够从源极通过真空通道到漏极发射。

9. 发明申请

US20120008395A1 Nonvolatile Memory Device and Method of Operating the Same 有权
标题翻译：非易失性存储器件及其操作方法
公开(公告)号：US20120008395A1
公开(公告)日：2012-01-12
申请号：US13176156
申请日：2011-07-05
申请人： Nam Kyeong Kim , Kyoung Chul Yang , Young Jin Woo , Tae Hyun Kim
发明人： Nam Kyeong Kim , Kyoung Chul Yang , Young Jin Woo , Tae Hyun Kim
IPC分类号： G11C16/16
CPC分类号： G11C16/16 , G11C16/0483
摘要： A nonvolatile memory device includes memory cell blocks each configured to comprise memory cells erased by an erase voltage, supplied to a word line, and a bulk voltage supplied to a bulk, a bias voltage generator configured to generate a first erase voltage, having a first pulse width and a first amplitude, in order to perform the erase operation of the memory cells and a second erase voltage, having a second pulse width narrower than the first pulse width and a second amplitude lower than the first amplitude, in order to perform an additional erase operation if an unerased memory cell is detected after the erase operation is performed, and a bulk voltage generator configured to generate the bulk voltage.
摘要翻译：非易失性存储器件包括存储单元块，每个存储单元块被配置为包括被提供给字线的擦除电压擦除的存储器单元和提供给块的体电压;偏置电压发生器，被配置为产生第一擦除电压，脉冲宽度和第一幅度，以便执行具有比第一脉冲宽度窄的第二脉冲宽度和低于第一幅度的第二幅度的存储单元的擦除操作和第二擦除电压，以便执行在执行擦除操作之后检测到未故障存储器单元的附加擦除操作，以及被配置为产生体电压的体电压发生器。

10. 发明授权

US07859120B2 Package system incorporating a flip-chip assembly 有权
标题翻译：封装系统采用倒装芯片组装
公开(公告)号：US07859120B2
公开(公告)日：2010-12-28
申请号：US12122631
申请日：2008-05-16
申请人： A Leam Choi , Young Jin Woo , Junwoo Myung
发明人： A Leam Choi , Young Jin Woo , Junwoo Myung
IPC分类号： H01L23/48
CPC分类号： H01L23/3135 , H01L21/563 , H01L21/565 , H01L23/13 , H01L23/3128 , H01L23/49827 , H01L23/5385 , H01L24/73 , H01L25/03 , H01L25/105 , H01L2224/05571 , H01L2224/05573 , H01L2224/16145 , H01L2224/16225 , H01L2224/1703 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73203 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2225/06558 , H01L2225/1023 , H01L2225/1058 , H01L2225/1088 , H01L2924/00014 , H01L2924/14 , H01L2924/15151 , H01L2924/15311 , H01L2924/1815 , H01L2924/19107 , H01L2924/3025 , H01L2924/00012 , H01L2924/00 , H01L2224/05599
摘要： A package system including providing a first semiconductor die; mounting a second semiconductor die on the first semiconductor die using an inter-die interconnect to form a flip-chip assembly; and attaching the flip-chip assembly on a package substrate with a contact pad, a test connection, a z-bond pad, and a die receptacle, with the first semiconductor die in the flip-chip assembly fitting inside the die receptacle.
摘要翻译：一种包装系统，包括提供第一半导体管芯; 使用晶片间互连来将第二半导体管芯安装在第一半导体管芯上以形成倒装芯片组件; 以及将所述倒装芯片组件安装在具有接触焊盘，测试连接件，z焊盘和模具插座的封装衬底上，所述倒装芯片组件中的所述第一半导体管芯装配在所述管芯插座内。

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