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1. 发明授权

US06226605B1 Digital voice processing apparatus providing frequency characteristic processing and/or time scale expansion 失效
标题翻译：提供频率特性处理和/或时标扩展的数字语音处理装置
公开(公告)号：US06226605B1
公开(公告)日：2001-05-01
申请号：US09132214
申请日：1998-08-11
申请人： Yoshito Nejime , Hiroshi Ikeda , Masao Hotta
发明人： Yoshito Nejime , Hiroshi Ikeda , Masao Hotta
IPC分类号： G10L1104
CPC分类号： H04R25/505 , G10L21/0232 , G10L21/0364 , G10L21/04 , H04R1/005 , H04R5/04 , H04R25/70 , H04R2205/041 , H04R2225/43
摘要： Making use of a digital acoustic signal processing apparatus arranged by employing memory device for storing a digital acoustic signal, acoustic frequency feature enhancing device for enhancing an acoustic frequency feature, and low-speed sound reproducing device for changing a speed of the stored voice to reproduce this voice as a low speed into a hearing aid and an appliance with an acoustic output, a hearing function difficulty due to an age is aided in utilization of audio output appliances such as a hearing aid, television receiver, and a telephone receiver. After the voice has been stored in the memory device, a process for enhancing the frequency characteristic in order to fit the frequency characteristic to the individual hearing characteristic and the voice reproducing environment is carried out and thereafter represented to the user. The user can repeatedly listen the voice stored in the memory device with employment of control device for controlling the voice reproducing operation. Furthermore, since a process for expanding a time scale during a sound reproducing operation is carried out, the voice can be represented at the low speed. Since the voice whose frequency characteristic has been enhanced can be represented at the low speed in order that either an individual hearing ability, or an apparatus is fitted to a using environment, hearing articulation can be improved with respect to such a hearing, the frequency resolution and the time resolution are simultaneously deteriorated.
摘要翻译：利用通过采用用于存储数字声音信号的存储装置而布置的数字声信号处理装置，用于增强声频特征的声频特征增强装置和用于改变所存储的声音的速度以便再现的低速声音再现装置这种声音作为低速进入助听器和具有声学输出的器具，由于年龄而引起的听力功能困难有助于使用诸如助听器，电视接收机和电话接收器的音频输出设备。在语音已被存储在存储装置中之后，执行用于增强频率特性以便将频率特性适应于个人听觉特性和语音再现环境的过程，并且此后表示给用户。用户可以通过使用用于控制语音再现操作的控制装置来重复监听存储在存储设备中的语音。此外，由于执行在声音再现操作期间扩展时标的处理，所以可以以低速表示声音。由于频率特性已被增强的声音可以以低速表示，以便将单独的听觉能力或装置安装在使用环境中，可以相对于这种听觉改善听觉发音，频率分辨率并且时间分辨率同时恶化。

2. 发明授权

US5794201A Digital acoustic signal processing apparatus 失效
标题翻译：数字声信号处理装置
公开(公告)号：US5794201A
公开(公告)日：1998-08-11
申请号：US462268
申请日：1995-06-05
申请人： Yoshito Nejime , Hiroshi Ikeda , Masao Hotta
发明人： Yoshito Nejime , Hiroshi Ikeda , Masao Hotta
IPC分类号： G10L21/02 , G10L21/0232 , G10L21/04 , H04R1/00 , H04R5/04 , H04R25/00 , G10L3/00 , G10L3/02 , G10L9/00
CPC分类号： H04R25/505 , G10L21/0364 , G10L21/04 , H04R1/005 , H04R5/04 , G10L21/0232 , H04R2205/041 , H04R2225/43 , H04R25/70
摘要： Making use of a digital acoustic signal processing apparatus arranged by employing memory device for storing a digital acoustic signal, acoustic frequency feature enhancing device for enhancing an acoustic frequency feature, and low-speed sound reproducing device for changing a speed of the stored voice to reproduce this voice as a low speed into a hearing aid and an appliance with an acoustic output, a hearing function difficulty due to an age is aided in utilization of audio output appliances such as a hearing aid, television receiver, and a telephone receiver. After the voice has been stored in the memory device, a process for enhancing the frequency characteristic in order to fit the frequency characteristic to the individual hearing characteristic and the voice reproducing environment is carried out and thereafter represented to the user. The user can repeatedly listen the voice stored in the memory device with employment of control device for controlling the voice reproducing operation. Furthermore, since a process for expanding a time scale during a sound reproducing operation is carried out, the voice can be represented at the low speed. Since the voice whose frequency characteristic has been enhanced can be represented at the low speed in order that either an individual hearing ability, or an apparatus is fitted to a using environment, hearing articulation can be improved with respect to such a hearing, the frequency resolution and the time resolution are simultaneously deteriorated.
摘要翻译：利用通过采用用于存储数字声音信号的存储装置而布置的数字声信号处理装置，用于增强声频特征的声频特征增强装置和用于改变所存储的声音的速度以便再现的低速声音再现装置这种声音作为低速进入助听器和具有声学输出的器具，由于年龄而引起的听力功能困难有助于使用诸如助听器，电视接收机和电话接收器的音频输出设备。在语音已被存储在存储装置中之后，执行用于增强频率特性以便将频率特性适应于个人听觉特性和语音再现环境的过程，并且此后表示给用户。用户可以通过使用用于控制语音再现操作的控制装置来重复监听存储在存储设备中的语音。此外，由于执行在声音再现操作期间扩展时标的处理，所以可以以低速表示声音。由于频率特性已被增强的声音可以以低速表示，以便将单独的听觉能力或装置安装到使用环境中，可以相对于这种听觉改善听觉发音，频率分辨率并且时间分辨率同时恶化。

3. 发明授权

US4939518A Analog to digital converter 失效
标题翻译：模数转换器
公开(公告)号：US4939518A
公开(公告)日：1990-07-03
申请号：US248374
申请日：1988-09-23
申请人： Masao Hotta , Toshihiko Shimizu , Kenzi Maio , Yoshito Nejime
发明人： Masao Hotta , Toshihiko Shimizu , Kenzi Maio , Yoshito Nejime
IPC分类号： H03M1/12 , H03M1/20 , H03M1/36
CPC分类号： H03M1/206 , H03M1/1235 , H03M1/365
摘要： In a cyclic averaging analog to digital converter, reference voltages having a plurality of levels, each of which is inputted to one of a plurality of comparators in a flash type analog to digital converter, are shifted cyclically by a small voltage, and the outputs of the flash type analog to digital converter are added for every shift cycle in order to obtain an output digital signal. The outputs of a voltage dividing circuit provide the reference voltages with N levels, the levels differing cyclically by a small voltage. The N reference voltages are divided into groups, each of which consists of M elements N/M, switches are provided each of which selects one of the reference voltages one after another for an associated group N/M reference voltages are thus selected by these switches and are supplied to the comparators.
摘要翻译：在循环平均模数转换器中，具有多个电平的参考电压，每个电平被输入到闪存类型模数转换器中的多个比较器中的一个，周期性地被小电压移位，并且输出为每个移位周期添加闪存型模数转换器，以获得输出数字信号。分压电路的输出为N个电平提供参考电压，该电平周期性地受到小电压的限制。 N个参考电压被分成组，每个组由M个元件N / M组成，提供开关，每个选择一个参考电压一个接一个地为相关联的组N / M参考电压由这些开关选择并提供给比较器。

4. 发明授权

US4866444A Analog-to-digital converter 失效
标题翻译：模数转换器
公开(公告)号：US4866444A
公开(公告)日：1989-09-12
申请号：US154086
申请日：1988-02-09
申请人： Yoshito Nejime , Masao Hotta , Kenji Maio , Koichi Ono
发明人： Yoshito Nejime , Masao Hotta , Kenji Maio , Koichi Ono
IPC分类号： H03M1/36 , H03M1/00 , H03M1/12
CPC分类号： H03M1/0809 , H03M1/365
摘要： A flash type AD converter includes a group of comparators divided into blocks each including 2.sup.N comparators (N=1, 2, ---), each comparing an input signal with one of a plurality of reference signals, each having individually different voltage levels. One of the comparators may correspond to a level change point where the voltage level of the input signal is higher than that of the reference signal of that comparator which then generates a specific output different from those of the remaining comparators. The converter generates a binary-coded output on the basis of the specific output generated from the level change point comparator. When any one of the plural comparators belonging to one of the blocks generates the specific output, the specific output is applied as an inhibit signal to inhibit appearance of an output from a block including comparators having reference voltage signals with corresponding levels lower than those of the comparators of the block to which the comparator generating the specific output belongs.
摘要翻译：闪光型AD转换器包括一组比较器，其被分成块，每个块包括2N个比较器（N = 1,2，...），每个比较器将输入信号与多个参考信号中的一个进行比较，每个参考信号具有单独不同的电压电平。一个比较器可以对应于电平变化点，其中输入信号的电压电平高于该比较器的参考信号的电平，然后产生与剩余的比较器不同的特定输出。转换器根据从电平变化点比较器产生的特定输出产生二进制编码输出。当属于其中一个块的多个比较器中的任何一个产生特定输出时，该特定输出被施加作为禁止信号，以抑制来自包括比较器的输出的出现，该比较器具有的参考电压信号的相应电平低于生成特定输出的比较器所属的块的比较器。

5. 发明授权

US5138203A Integrated circuit compensation for losses in signal lines due to parasitics 失效
标题翻译：由于寄生效应引起的信号线损耗的集成电路补偿
公开(公告)号：US5138203A
公开(公告)日：1992-08-11
申请号：US342328
申请日：1989-04-24
申请人： Koichi Ono , Masao Hotta , Yoshito Nejime
发明人： Koichi Ono , Masao Hotta , Yoshito Nejime
IPC分类号： H03M1/36 , H03K17/16 , H03K17/60 , H03K19/0175 , H03M1/06
CPC分类号： H03M1/06 , H03K17/16 , H03K17/603 , H03M1/365
摘要： An integrated circuit including a plurality of circuits having the same input impedance, arranged at regular intervals, and applied with a signal from a single signal source, is disclosed in which the input impedance is substantially capacitive, the characteristic impedance of a signal line connected to the signal source for sending the signal to the circuits is given by Z.sub.0 .sqroot.L/C, where L indicates the inductance of the signal line per one circuit, and C indicates the combined capacitance of the parasitic capacitance of the signal line per one circuit and the input capacitance of each circuit, the signal line is terminated by a circuit element having impedance equal to the characteristic impedance Z.sub.0, and the signal source has output impedance equal to the characteristic impedance Z.sub.0.
摘要翻译：公开了一种集成电路，其包括具有相同输入阻抗的多个电路，以规则的间隔布置并且施加了来自单个信号源的信号，其中输入阻抗基本上是电容性的，信号线的特性阻抗连接到用于将信号发送到电路的信号源由Z0 2ROOT L / C给出，其中L表示每个电路的信号线的电感，C表示每个电路的信号线的寄生电容的组合电容，每个电路的输入电容，信号线由具有等于特性阻抗Z0的阻抗的电路元件端接，并且信号源具有等于特性阻抗Z0的输出阻抗。

6. 发明授权

US4978957A High-speed analog-to-digital converter 失效
标题翻译：高速模数转换器
公开(公告)号：US4978957A
公开(公告)日：1990-12-18
申请号：US475799
申请日：1990-02-06
申请人： Masao Hotta , Toshihiko Shimizu , Yoshito Nejime
发明人： Masao Hotta , Toshihiko Shimizu , Yoshito Nejime
IPC分类号： H03M1/14 , H03M1/36
CPC分类号： H03M1/147 , H03M1/365
摘要： Disclosed is a parallel analog-to-digital converter in which a plurality of comparators are divided into a plurality of groups each consisting of a predetermined number of comparators, and outputs of at least these comparators belonging to the same group are added in an analog or digital fashion. Whether or not the result of addition of the outputs of the comparators exceeds a predetermined threshold level is decided in an analog or digital fashion so as to determine high-order and low-order bits of a digital output signal of the converter on the basis of the result of decision.
摘要翻译：公开了一种并行模拟 - 数字转换器，其中多个比较器被分成多个组，每个组由预定数量的比较器组成，并且至少属于同一组的这些比较器的输出被添加到模拟或数码时尚。以模拟或数字的方式决定比较器的输出的相加结果是否超过预定阈值水平，以便基于以下方式确定转换器的数字输出信号的高阶和低位：决定的结果。

7. 发明授权

US07366489B2 Mobile communication apparatus 有权
标题翻译：移动通信装置
公开(公告)号：US07366489B2
公开(公告)日：2008-04-29
申请号：US10742813
申请日：2003-12-23
申请人： Satoshi Tanaka , Kazuo Watanabe , Masao Hotta , Toyohiko Hongo , Taizo Yamawaki , Masumi Kasahara , Kumiko Takikawa
发明人： Satoshi Tanaka , Kazuo Watanabe , Masao Hotta , Toyohiko Hongo , Taizo Yamawaki , Masumi Kasahara , Kumiko Takikawa
IPC分类号： H04B1/06 , H04B1/10
CPC分类号： H04B1/30 , H03D2200/0047 , H03K21/16
摘要： A transceiver suitable for larger scale of integration employs direct conversion reception for reducing the number of filters. Also, the number of VCOs is reduced by utilizing dividers to supply a receiver and a transmitter with locally oscillated signals at an RF band. Dividers each having a fixed division ratio are used for generating locally oscillated signals for the receiver, while a divider having a switchable division ratio are used for generating the locally oscillated signal for the transmitter. In addition, a variable gain amplifier for baseband signal is provided with a DC offset voltage detector and a DC offset canceling circuit for supporting high speed data communications to accomplish fast cancellation of a DC offset by eliminating intervention of a filter within a feedback loop for offset cancellation.
摘要翻译：适合较大规模集成的收发器采用直接转换接收，以减少滤波器的数量。此外，通过利用分频器来为RF频带提供具有本地振荡信号的接收机和发射机来减少VCO的数量。每个具有固定分频比的分频器用于产生用于接收机的局部振荡信号，而具有可切换分频比的分频器用于产生用于发射机的本地振荡信号。另外，用于基带信号的可变增益放大器设置有DC偏移电压检测器和DC偏移消除电路，用于支持高速数据通信以通过消除用于偏移的反馈回路内的滤波器的干涉来实现DC偏移的快速消除消除。

8. 发明授权

US5291135A Weak magnetic field measuring system using dc-SQUID magnetometer with bias current adjustment and/or detecting function of abnormal operation 失效
标题翻译：使用具有偏置电流调节和/或检测异常运行功能的dc-SQUID磁力计的弱磁场测量系统
公开(公告)号：US5291135A
公开(公告)日：1994-03-01
申请号：US767667
申请日：1991-09-30
申请人： Masao Hotta , Hisashi Kado , Keiko Makie
发明人： Masao Hotta , Hisashi Kado , Keiko Makie
IPC分类号： G01R33/035
CPC分类号： G01R33/0356 , Y10S505/846
摘要： A multichannel weak magnetic field measuring system for neuromagnetic diagnosis is provided having a plurality of dc-SQUID magnetometers. Bias current setting circuits are provided for detecting an even harmonic component of the output across the terminals of the corresponding SQUID and automatically adjusting a DC bias current to the SQUID. Accordingly, the level of the component becomes a predetermined value. Circuitry is also included for equalizing the magnetic flux detection sensitivities of these dc-SQUID magnetometers. Abnormal operation detecting circuits are also provided for producing abnormal operation detected outputs when the level of the corresponding even harmonic component is smaller than a certain threshold value.
摘要翻译：提供了具有多个dc-SQUID磁力计的用于神经磁性诊断的多通道弱磁场测量系统。提供偏置电流设定电路，用于检测相应SQUID两端的输出的均匀谐波分量，并自动调整到SQUID的直流偏置电流。因此，部件的电平成为规定值。还包括电路用于均衡这些dc-SQUID磁力计的磁通检测灵敏度。当相应的偶次谐波分量的电平小于某个阈值时，还提供异常运行检测电路用于产生异常运行检测输出。

9. 发明授权

US5113077A Radiation detection circuit having a signal integrating capacitor, and a data aquisition system for an X-ray scanner including such circuit 失效
标题翻译：具有信号积分电容器的辐射检测电路和包括这种电路的X射线扫描仪的数据采集系统
公开(公告)号：US5113077A
公开(公告)日：1992-05-12
申请号：US588718
申请日：1990-09-27
申请人： Toshihiko Shimizu , Masao Hotta , Atsushi Moritani
发明人： Toshihiko Shimizu , Masao Hotta , Atsushi Moritani
IPC分类号： A61B6/03 , G01T1/17 , G01T1/20 , G01T1/29
CPC分类号： G01T1/17 , G01T1/2985
摘要： A radiation detection circuit integrates output currents of a plurality of X-ray CT scanner radiation detectors, which are combinations of scintillators and photodiodes, during a short period to convert them to charge information in order to collect data for reproducing a tomogram. A current amplifier is connected to the output terminal of the photo-diode, and an output current of the current amplifier is charged in an integration capacitor. In this manner, the radiation detection circuit enables reduction of the measurement period.
摘要翻译：辐射检测电路在短时间内将作为闪烁体和光电二极管的组合的多个X射线CT扫描仪辐射检测器的输出电流进行积分，以将其转换为电荷信息，以便收集用于再现断层图像的数据。电流放大器连接到光电二极管的输出端，并且电流放大器的输出电流在积分电容器中充电。以这种方式，辐射检测电路能够减少测量周期。

10. 发明申请

US20110090103A1 ANALOG-TO-DIGITAL CONVERTER 失效
标题翻译：模拟数字转换器
公开(公告)号：US20110090103A1
公开(公告)日：2011-04-21
申请号：US12907629
申请日：2010-10-19
申请人： Masao Hotta , Tatsuji Matsuura
发明人： Masao Hotta , Tatsuji Matsuura
IPC分类号： H03M1/00
CPC分类号： H03M1/144
摘要： A sequential comparison-type analog-to-digital converter (ADC) that has improved precision and which is capable of high-speed operation is disclosed, the analog-to-digital converter comprising a digital-to-analog converter that outputs a plurality of different reference analog signals according to a multibit digital signal, a plurality of comparators that compare an input analog signal with the plurality of reference analog signals, and a sequential comparison control circuit that changes bit values of the multibit digital signal in order from higher bits so that at least one of the plurality of reference analog signals becomes closer to the input analog signal and decides the bit values in order from higher bits based on the comparison results and at the same time, correcting the decided higher bit values, wherein the sequential comparison control circuit decides the bit values of the multibit digital signal down to a predetermined bit based on the comparison results of the plurality of comparators and at the same time, correcting the bit values, and decides the bits lower than the predetermined bit based on the comparison result of one of the plurality of comparators.
摘要翻译：公开了一种具有改进的精度并且能够进行高速操作的顺序比较型模数转换器（ADC），该模数转换器包括数/模转换器，其输出多个根据多位数字信号的不同参考模拟信号，将输入模拟信号与多个参考模拟信号进行比较的多个比较器，以及从高位开始依次改变多位数字信号的位值的顺序比较控制电路多个参考模拟信号中的至少一个变得更靠近输入模拟信号，并且基于比较结果从较高位确定比特值，并且同时校正所确定的较高比特值，其中顺序比较控制电路基于多个比较结果将多位数字信号的位值判定为预定位并且同时校正位值，并且基于多个比较器之一的比较结果来确定比预定位低的位。

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