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1. 发明申请

US20080046637A1 Semiconductor Device and Processing Method for Starting the Same 有权
标题翻译：用于启动它的半导体器件和处理方法
公开(公告)号：US20080046637A1
公开(公告)日：2008-02-21
申请号：US10597353
申请日：2005-01-27
申请人： Yoshito Katano , Tadashi Yoshida , Kazuhiro Sako
发明人： Yoshito Katano , Tadashi Yoshida , Kazuhiro Sako
IPC分类号： G06F12/00
CPC分类号： G06F11/1417 , G06F11/1666 , G06F11/20
摘要： A flash memory is made to store a same boot program in a plurality of blocks in it. When a flash memory controller receives an access command for accessing the storage region storing the boot program from a CPU (Step S101), it outputs the read out data to the CPU only when the corresponding block is not faulty according to the determination (Steps S105, S106) made on the basis of the ECC contained in the data read out from the corresponding page and the determination (Step S109) made on the basis of the block information also contained in the data read out from the corresponding page. If, on the other hand it is determined that the block is faulty, the flash memory controller reads out the boot program stored in the next block (Steps S106, S103) and determines once again that the block is faulty or not faulty.
摘要翻译：闪速存储器将相同的引导程序存储在其中的多个块中。当闪速存储器控制器从CPU接收访问存储引导程序的存储区域的访问命令时（步骤S101），仅当相应的块根据该确定没有故障时才将读出的数据输出到CPU（步骤 S 105，S 106），并且根据从相应页面读出的数据中还包含的块信息进行的确定（步骤S109），进行基于包含在从相应页面读出的数据中的ECC 。另一方面，如果确定块有故障，则闪存控制器读出存储在下一块中的引导程序（步骤S106，S103），并再次确定该块是有故障的还是不存在的。

2. 发明授权

US08135991B2 Semiconductor device and processing method for starting the same 有权
标题翻译：半导体装置及其起动方法
公开(公告)号：US08135991B2
公开(公告)日：2012-03-13
申请号：US10597353
申请日：2005-01-27
申请人： Yoshito Katano , Tadashi Yoshida , Kazuhiro Sako
发明人： Yoshito Katano , Tadashi Yoshida , Kazuhiro Sako
IPC分类号： G06F11/00
CPC分类号： G06F11/1417 , G06F11/1666 , G06F11/20
摘要： A flash memory is made to store a same boot program in a plurality of blocks in it. When a flash memory controller receives an access command for accessing the storage region storing the boot program from a CPU (Step S101), it outputs the read out data to the CPU only when the corresponding block is not faulty according to the determination (Steps S105, S106) made on the basis of the ECC contained in the data read out from the corresponding page and the determination (Step S109) made on the basis of the block information also contained in the data read out from the corresponding page. If, on the other hand it is determined that the block is faulty, the flash memory controller reads out the boot program stored in the next block (Steps S106, S103) and determines once again that the block is faulty or not faulty.
摘要翻译：闪速存储器将相同的引导程序存储在其中的多个块中。当闪存控制器从CPU接收访问存储引导程序的存储区域的访问命令时（步骤S101），只有当相应的程序段根据该确定没有故障时才将该读出的数据输出到CPU（步骤S105 ，S106）基于从相应页面读出的数据中包含的ECC进行的判定（步骤S109），以及基于从相应页面读出的数据中包含的块信息进行的确定（步骤S109）。另一方面，如果确定块是故障的，则闪存控制器读出存储在下一块中的引导程序（步骤S106，S103），并再次确定块是有故障的还是不存在的。

3. 发明授权

US08601191B2 Bus system and deadlock avoidance circuit thereof 有权
标题翻译：总线系统及其死锁回避电路
公开(公告)号：US08601191B2
公开(公告)日：2013-12-03
申请号：US13137191
申请日：2011-07-27
申请人： Sumie Aoki , Yoshito Katano
发明人： Sumie Aoki , Yoshito Katano
IPC分类号： G06F13/14 , G06F13/40 , G06F13/16
CPC分类号： G06F13/4036 , G06F13/1621 , G06F13/1626 , G06F13/366 , G06F13/4022
摘要： Disclosed herein is a deadlock avoidance circuit including: a previous-transaction-information management section; a transaction-issuance-termination determination section; and a response-outputting control section.
摘要翻译：这里公开了一种死锁回避电路，包括：先前交易信息管理部分; 交易发行终止确定部分; 和响应输出控制部。

4. 发明申请

US20090319730A1 MEMORY SYSTEM, ACCESS CONTROL METHOD THEREFOR, AND COMPUTER PROGRAM 有权
标题翻译：存储系统，其访问控制方法和计算机程序
公开(公告)号：US20090319730A1
公开(公告)日：2009-12-24
申请号：US12485214
申请日：2009-06-16
申请人： Hideo Tanaka , Yoshito Katano
发明人： Hideo Tanaka , Yoshito Katano
IPC分类号： G06F12/00 , G06F13/36 , G06F13/14
CPC分类号： G06F13/4243
摘要： A memory system includes: a memory that has plural banks; a memory controller that includes a request queue and a bank monitor and controls access to the memory; a master group including plural masters that can request access to the memory; and a system bus which is connected between the memory controller and the master group and in which an arbiter is arranged, wherein the request queue has a scheduling function for receiving access requests issued from the master group through the system bus and appropriately rearranging the received access requests and provides the arbiter with queue information, the bank monitor monitors information concerning respective banks of the memory and provides the arbiter with the bank information, and the arbiter arbitrates requests issued in parallel from the masters of the master group on the basis of the queue information and the bank information provided thereto and transmits the information to the memory controller as access control information.
摘要翻译：存储器系统包括：具有多个存储体的存储器; 存储器控制器，其包括请求队列和存储体监视器，并控制对存储器的访问; 包括可以请求访问存储器的多个主器件的主组; 以及系统总线，其连接在所述存储器控制器和所述主组之间，并且其中布置有仲裁器，其中所述请求队列具有用于通过所述系统总线接收从所述主组发出的访问请求的调度功能，并且适当地重新排列所接收的访问请求并向仲裁者提供队列信息，银行监视器监视与存储器的各个存储体相关的信息，并向仲裁者提供银行信息，并且仲裁者根据该队列仲裁从主组的主人并行发出的请求信息和提供给其的银行信息，并将该信息作为访问控制信息发送到存储器控制器。

5. 发明授权

US08200882B2 Memory system, access control method therefor, and computer program 有权
标题翻译：内存系统，访问控制方法和计算机程序
公开(公告)号：US08200882B2
公开(公告)日：2012-06-12
申请号：US12485214
申请日：2009-06-16
申请人： Hideo Tanaka , Yoshito Katano
发明人： Hideo Tanaka , Yoshito Katano
IPC分类号： G06F12/00
CPC分类号： G06F13/4243
摘要： A memory system includes: a memory that has plural banks; a memory controller that includes a request queue and a bank monitor and controls access to the memory; a master group including plural masters that can request access to the memory; and a system bus which is connected between the memory controller and the master group and in which an arbiter is arranged, wherein the request queue has a scheduling function for receiving access requests issued from the master group through the system bus and appropriately rearranging the received access requests and provides the arbiter with queue information, the bank monitor monitors information concerning respective banks of the memory and provides the arbiter with the bank information, and the arbiter arbitrates requests issued in parallel from the masters of the master group on the basis of the queue information and the bank information provided thereto and transmits the information to the memory controller as access control information.
摘要翻译：存储器系统包括：具有多个存储体的存储器; 存储器控制器，其包括请求队列和存储体监视器，并控制对存储器的访问; 包括可以请求访问存储器的多个主器件的主组; 以及系统总线，其连接在所述存储器控制器和所述主组之间，并且其中布置有仲裁器，其中所述请求队列具有用于通过所述系统总线接收从所述主组发出的访问请求的调度功能，并且适当地重新排列所接收的访问请求并向仲裁者提供队列信息，银行监视器监视与存储器的各个存储体相关的信息，并向仲裁者提供银行信息，并且仲裁者根据该队列仲裁从主组的主人并行发出的请求信息和提供给其的银行信息，并将该信息作为访问控制信息发送到存储器控制器。

6. 发明申请

US20120079150A1 Bus system and deadlock avoidance circuit thereof 有权
标题翻译：总线系统及其死锁回避电路
公开(公告)号：US20120079150A1
公开(公告)日：2012-03-29
申请号：US13137191
申请日：2011-07-27
申请人： Sumie Aoki , Yoshito Katano
发明人： Sumie Aoki , Yoshito Katano
IPC分类号： G06F13/00
CPC分类号： G06F13/4036 , G06F13/1621 , G06F13/1626 , G06F13/366 , G06F13/4022
摘要： Disclosed herein is a deadlock avoidance circuit including: a previous-transaction-information management section; a transaction-issuance-termination determination section; and a response-outputting control section.
摘要翻译：这里公开了一种死锁回避电路，包括：先前交易信息管理部分; 交易发行终止确定部分; 和响应输出控制部。

7. 发明授权

US06748406B2 Bit search device and bit search method 失效
标题翻译：位搜索设备和位搜索方式
公开(公告)号：US06748406B2
公开(公告)日：2004-06-08
申请号：US10179192
申请日：2002-06-26
申请人： Yoshito Katano
发明人： Yoshito Katano
IPC分类号： G06F1500
CPC分类号： G06F7/74
摘要： When one clock signal (CLK) is output, the following operations are performed: an input data signal D is latched by a data latch; a detection-type signal K is latched by a signal latch; the input data signal D is input to a 1 detecting circuit and a 0 detecting circuit, which are connected in parallel, while the data latch holds the input data signal D; for example, a 1 detection process for detecting that bit data changes from 0 to 1 or a 0 detection process for detecting that bit data changes from 1 to 0 is performed; and either a 1 detection or a 0 detection output operation, which is selected by a selector circuit 27, is performed. As a result, a bit search process is quickly performed.
摘要翻译：当输出一个时钟信号（CLK）时，执行以下操作：输入数据信号D被数据锁存器锁存; 检测型信号K由信号锁存器锁存; 输入数据信号D输入到并行连接的1检测电路和0检测电路，同时数据锁存器保持输入数据信号D; 例如，执行用于检测位数据从0变为1的1检测处理或用于检测位数据从1变为0的0检测处理; 并且执行由选择器电路27选择的1检测或0检测输出操作。结果，快速执行位搜索处理。

8. 发明授权

US06560622B2 Bit search device and bit search method 失效
公开(公告)号：US06560622B2
公开(公告)日：2003-05-06
申请号：US09318616
申请日：1999-05-26
申请人： Yoshito Katano
发明人： Yoshito Katano
IPC分类号： G06F700
CPC分类号： G06F7/74
摘要： When one clock signal (CLK) is output, the following operations are performed: an input data signal D is latched by a data latch; a detection-type signal K is latched by a signal latch; the input data signal D is input to a 1 detecting circuit and a 0 detecting circuit, which are connected in parallel, while the data latch holds the input data signal D; for example, a 1 detection process for detecting that bit data changes from 0 to 1 or a 0 detection process for detecting that bit data changes from 1 to 0 is performed; and either a 1 detection or a 0 detection output operation, which is selected by a selector circuit 27, is performed. As a result, a bit search process is quickly performed.

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