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1. 发明申请

US20110013696A1 MOVING IMAGE PROCESSOR AND PROCESSING METHOD FOR MOVING IMAGE 有权
标题翻译：移动图像处理器和移动图像的处理方法
公开(公告)号：US20110013696A1
公开(公告)日：2011-01-20
申请号：US12819394
申请日：2010-06-21
申请人： Yoshitaka HIRAMATSU , Hiroaki NAKATA , Masakazu EHAMA , Seiji MOCHIZUKI , Takafumi YUASA , Kenichi IWATA
发明人： Yoshitaka HIRAMATSU , Hiroaki NAKATA , Masakazu EHAMA , Seiji MOCHIZUKI , Takafumi YUASA , Kenichi IWATA
IPC分类号： H04N7/26 , H04N7/32 , H04N11/02
CPC分类号： H04N19/86 , H04N19/423 , H04N19/436
摘要： A moving image processor includes a first and a second moving image processing unit which are able to perform parallel operation, and a data transfer unit having a first buffer and a second buffer. The first moving image processing unit processes macroblocks MB00, - - - , of one row of one image sequentially, and the second moving image processing unit processes macroblocks MB10, - - - , of the next row sequentially. The first and the second moving image processors include a first and a second deblocking filters, respectively. Operation timing of the second filter is delayed by the processing time of two macroblocks, compared with operation timing of the first filter. The processing results of the first filter and the second filter are transferred to an external memory via the first buffer and the second buffer of the transfer unit.
摘要翻译：运动图像处理器包括能够执行并行操作的第一和第二运动图像处理单元，以及具有第一缓冲器和第二缓冲器的数据传送单元。第一运动图像处理单元顺序地处理一行一个图像的宏块MB00，...，并且第二运动图像处理单元依次处理下一行的宏块MB10， - - - 。第一和第二运动图像处理器分别包括第一和第二去块滤波器。与第一滤波器的操作定时相比，第二滤波器的操作定时被延迟两个宏块的处理时间。第一滤波器和第二滤波器的处理结果经由传送单元的第一缓冲器和第二缓冲器传送到外部存储器。

2. 发明申请

US20120263233A1 DATA PROCESSING CIRCUIT 审中-公开
标题翻译：数据处理电路
公开(公告)号：US20120263233A1
公开(公告)日：2012-10-18
申请号：US13533570
申请日：2012-06-26
申请人： Kenichi IWATA , Seiji Mochizuki , Tetsuya Shibayama , Fumitaka Izuhara , Hiroshi Ueda , Yukifumi Kobayashi , Hiroaki Nakata , Koji Hosogi , Masakazu Ehama , Takafumi Yuasa
发明人： Kenichi IWATA , Seiji Mochizuki , Tetsuya Shibayama , Fumitaka Izuhara , Hiroshi Ueda , Yukifumi Kobayashi , Hiroaki Nakata , Koji Hosogi , Masakazu Ehama , Takafumi Yuasa
IPC分类号： H04N7/26 , H04N7/32
CPC分类号： H04N19/436 , H04N19/176 , H04N19/593
摘要： The present invention provides a functional block that executes video coding and video decoding based on H. 264/AVC. The functional block includes two moving picture processing units, and a memory unit that stores therein data related to the results of processing of first plural macroblocks arranged within one row of one picture by the first moving picture processing unit. Data related to the results of processing of plural adjacent macroblocks, which are selected from the data stored in the memory unit, are transferred to the second moving picture processing unit. The second moving picture processing unit performs processing of one macroblock of second plural macroblocks arranged in the following row, using the transferred data.
摘要翻译：本发明提供一种执行基于H.264 / AVC的视频编码和视频解码的功能块。功能块包括两个运动图像处理单元，以及存储单元，其存储与第一运动图像处理单元一行布置在一行内的第一多个宏块的处理结果有关的数据。与从存储在存储单元中的数据中选择的多个相邻宏块的处理结果有关的数据被传送到第二运动图像处理单元。第二运动图像处理单元使用传送的数据来执行排列在下一行中的第二多个宏块的一个宏块的处理。

3. 发明申请

US20080031329A1 DATA PROCESSING CIRCUIT 失效
标题翻译：数据处理电路
公开(公告)号：US20080031329A1
公开(公告)日：2008-02-07
申请号：US11834449
申请日：2007-08-06
申请人： Kenichi IWATA , Seiji Mochizuki , Tetsuya Shibayama , Fumitaka Izuhara , Hiroshi Ueda , Yukifumi Kobayashi , Hiroaki Nakata , Koji Hosogi , Masakazu Ehama , Takafumi Yuasa
发明人： Kenichi IWATA , Seiji Mochizuki , Tetsuya Shibayama , Fumitaka Izuhara , Hiroshi Ueda , Yukifumi Kobayashi , Hiroaki Nakata , Koji Hosogi , Masakazu Ehama , Takafumi Yuasa
IPC分类号： H04N7/32
CPC分类号： H04N19/436 , H04N19/176 , H04N19/593
摘要： The present invention provides a functional block that executes video coding and video decoding based on H.264/AVC. The functional block includes two moving picture processing units, and a memory unit that stores therein data related to the results of processing of first plural macroblocks arranged within one row of one picture by the first moving picture processing unit. Data related to the results of processing of plural adjacent macroblocks, which are selected from the data stored in the memory unit, are transferred to the second moving picture processing unit. The second moving picture processing unit performs processing of one macroblock of second plural macroblocks arranged in the following row, using the transferred data.
摘要翻译：本发明提供一种执行基于H.264 / AVC的视频编码和视频解码的功能块。功能块包括两个运动图像处理单元，以及存储单元，其存储与第一运动图像处理单元一行布置在一行内的第一多个宏块的处理结果有关的数据。与从存储在存储单元中的数据中选择的多个相邻宏块的处理结果有关的数据被传送到第二运动图像处理单元。第二运动图像处理单元使用传送的数据来执行排列在下一行中的第二多个宏块的一个宏块的处理。

4. 发明申请

US20090245664A1 IMAGE ENCODING DEVICE 有权
标题翻译：图像编码装置
公开(公告)号：US20090245664A1
公开(公告)日：2009-10-01
申请号：US12401613
申请日：2009-03-10
申请人： Keisuke MATSUMOTO , Seiji MOCHIZUKI , Kenichi IWATA , Fumitaka IZUHARA , Motoki KIMURA
发明人： Keisuke MATSUMOTO , Seiji MOCHIZUKI , Kenichi IWATA , Fumitaka IZUHARA , Motoki KIMURA
IPC分类号： G06K9/36
CPC分类号： H04N19/86 , H04N19/103 , H04N19/124 , H04N19/17 , H04N19/176 , H04N19/436 , H04N19/61
摘要： The present invention provides an image encoding device which does not necessitate reference of a quantization parameter between consecutive macroblocks across a parallel processing area boundary without forming slices. The image encoding device encodes a macroblock of an encoding target image by parallel processing sequentially from the top of a parallel processing area, and possesses an encoding element for every parallel processing area. When all the quantized orthogonally-transformed coefficients of a top macroblock of the parallel processing area are zero, the encoding element adds a non-zero coefficient to a part of the coefficients, making the coefficients non-zero. Accordingly, generation of a skip macroblock in the top macroblock of each parallel processing area is suppressed. Since slice formation is not necessary, the prediction over a parallel processing area boundary is applied, and encoding efficiency improves. Errors are not generated in decoding and the decoded image quality does not deteriorate.
摘要翻译：本发明提供一种图像编码装置，其不需要跨并行处理区域边界的连续宏块之间的量化参数的引用而不形成切片。图像编码装置通过从并行处理区域的顶部顺序并行处理对编码对象图像的宏块进行编码，并具有每个并行处理区域的编码元素。当并行处理区域的顶部宏块的所有量化的正交变换系数为零时，编码元件将一个非零系数加到系数的一部分，使系数不为零。因此，抑制了每个并行处理区域的顶部宏块中的跳过宏块的生成。由于不需要切片形成，因此应用了并行处理区域边界的预测，并且提高了编码效率。在解码中不产生错误，解码的图像质量不会恶化。

5. 发明申请

US20090245662A1 DATA PROCESSING DEVICE, IMAGE ENCODING/DECODING DEVICE AND DATA PROCESSING SYSTEM 失效
标题翻译：数据处理设备，图像编码/解码设备和数据处理系统
公开(公告)号：US20090245662A1
公开(公告)日：2009-10-01
申请号：US12399956
申请日：2009-03-08
申请人： Hiroshi UEDA , Kenichi IWATA , Seiji MOCHIZUKI
发明人： Hiroshi UEDA , Kenichi IWATA , Seiji MOCHIZUKI
IPC分类号： G06K9/36 , G06F15/76 , G06F9/06
CPC分类号： H04N19/12 , G06F9/50 , H04N19/436
摘要： To reduce a processing load of an external CPU, when a large amount of data is initially set frequently to an image coding/decoding device. The image encoding/decoding device (data processing device) includes a first circuit and a second circuit for providing initial setting to a plurality of image processing modules (processor units), wherein the image encoding/decoding device does not receive information, which is initially set to the image processing modules, directly from the external CPU, and control information for the initial setting is set to the first circuit from the CPU. The second circuit reads in initial setting information and setting-target information of the initial setting information from outside using the control information set in the first circuit and transfers the initial setting information to the image processing module according to the read-in setting-target information. The CPU does not need to set the whole information, which is initially set to the image processing modules, directly to the image encoding/decoding device, and also does not need to set both of a transfer source address and a transfer destination address which are required as in a case of utilizing DMA transfer.
摘要翻译：为了减少外部CPU的处理负担，当大量的数据最初被频繁地设置到图像编码/解码装置时。图像编码/解码装置（数据处理装置）包括第一电路和第二电路，用于向多个图像处理模块（处理器单元）提供初始设置，其中图像编码/解码装置不接收最初的信息设置为图像处理模块，直接从外部CPU，初始设置的控制信息设置为CPU的第一个电路。第二电路使用在第一电路中设置的控制信息从外部读入初始设置信息和初始设置信息的设置目标信息，并根据读入设置目标信息将初始设置信息传送到图像处理模块。 CPU不需要将初始设置为图像处理模块的整个信息直接设置到图像编码/解码装置，也不需要设置传送源地址和传送目的地地址在使用DMA传输的情况下需要。

6. 发明申请

US20120232727A1 CONTROL DEVICE FOR PROPULSION MACHINE 有权
标题翻译：推进机控制装置
公开(公告)号：US20120232727A1
公开(公告)日：2012-09-13
申请号：US13204303
申请日：2011-08-05
申请人： Kenichi IWATA , Makoto ITOI
发明人： Kenichi IWATA , Makoto ITOI
IPC分类号： B63H21/21
CPC分类号： B63H21/21 , B60W10/06 , B63H21/213 , B63H2020/003 , B63H2021/216
摘要： A control device controls the operating state of each of a plurality of propulsion machines arranged in parallel in a marine vessel. Control devices are connected to each other by a communication line through which operating information of the propulsion machine is mutually transmitted and received. The control device includes a unit which determines the installation position of a corresponding propulsion machine, a unit which determines the connection state of another propulsion machine connected to the communication line, and a unit which determines a propulsion machine as a control reference from among a plurality of control devices. The propulsion machine as a control reference is switched to a propulsion machine which is arbitrarily designated by an operator or a propulsion machine which has the highest priority as a control reference.
摘要翻译：控制装置控制在船舶中平行布置的多个推进机中的每一个的操作状态。控制装置通过通信线彼此连接，通过该通信线路，推进机的操作信息被相互传送和接收。控制装置包括确定对应的推进机的安装位置的单元，确定连接到通信线路的另一个推进机的连接状态的单元以及从多个之间确定作为控制参考的推进机的单元的控制装置。作为控制基准的推进机切换到作为控制基准的作业员或具有最高优先级的推进机任意指定的推进机。

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