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1. 发明申请

US20090201753A1 Semiconductor memory device, control method therefor, and method for determining repair possibility of defective address 有权
标题翻译：半导体存储器件及其控制方法以及用于确定缺陷地址修复可能性的方法
公开(公告)号：US20090201753A1
公开(公告)日：2009-08-13
申请号：US12320892
申请日：2009-02-06
申请人： Yoshiro Riho , Jun Suzuki , Yasuhiro Matsumoto , Shuichi Kubouchi , Hiromasa Noda , Yasuji Koshikawa
发明人： Yoshiro Riho , Jun Suzuki , Yasuhiro Matsumoto , Shuichi Kubouchi , Hiromasa Noda , Yasuji Koshikawa
IPC分类号： G11C29/00 , G11C8/00 , G11C17/16
CPC分类号： G11C8/08 , G11C8/10 , G11C29/84
摘要： There are provided are a plurality of memory mats, a sub-word driver that accesses a normal memory cell irrespective of whether a row address to which access is requested is a defective address, a sub-word driver that accesses a redundant memory cell belonging to a memory mat different from the normal memory cell indicated by the row address, when the row address is a defective address. According to the present invention, the normal memory cell and a redundant memory cell belong to memory mats different to each other, and thus the normal memory cell can be accessed concurrently with determining operation of the repair determining circuit.
摘要翻译：提供有多个存储器垫，子字驱动器，其访问正常存储器单元，而不管请求访问的行地址是否是缺陷地址;子字驱动器，访问属于当行地址是缺陷地址时，由行地址指示的正常存储单元不同的存储器垫。根据本发明，正常存储单元和冗余存储单元属于彼此不同的存储器单元，从而可以在确定修复确定电路的操作的同时访问正常存储单元。

2. 发明授权

US07940583B2 Semiconductor memory device, control method therefor, and method for determining repair possibility of defective address 有权
标题翻译：半导体存储器件及其控制方法以及用于确定缺陷地址修复可能性的方法
公开(公告)号：US07940583B2
公开(公告)日：2011-05-10
申请号：US12320892
申请日：2009-02-06
申请人： Yoshiro Riho , Jun Suzuki , Yasuhiro Matsumoto , Shuichi Kubouchi , Hiromasa Noda , Yasuji Koshikawa
发明人： Yoshiro Riho , Jun Suzuki , Yasuhiro Matsumoto , Shuichi Kubouchi , Hiromasa Noda , Yasuji Koshikawa
IPC分类号： G11C29/00
CPC分类号： G11C8/08 , G11C8/10 , G11C29/84
摘要： There are provided are a plurality of memory mats, a sub-word driver that accesses a normal memory cell irrespective of whether a row address to which access is requested is a defective address, a sub-word driver that accesses a redundant memory cell belonging to a memory mat different from the normal memory cell indicated by the row address, when the row address is a defective address. According to the present invention, the normal memory cell and a redundant memory cell belong to memory mats different to each other, and thus the normal memory cell can be accessed concurrently with determining operation of the repair determining circuit.
摘要翻译：提供有多个存储器垫，子字驱动器，其访问正常存储器单元，而不管请求访问的行地址是否是缺陷地址;子字驱动器，访问属于当行地址是缺陷地址时，由行地址指示的正常存储单元不同的存储器垫。根据本发明，正常存储单元和冗余存储单元属于彼此不同的存储器单元，从而可以在确定修复确定电路的操作的同时访问正常存储单元。

3. 发明授权

US08411522B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08411522B2
公开(公告)日：2013-04-02
申请号：US13311344
申请日：2011-12-05
申请人： Yasuhiro Matsumoto , Yasuji Koshikawa
发明人： Yasuhiro Matsumoto , Yasuji Koshikawa
IPC分类号： G11C7/02
CPC分类号： H01L27/0207 , H01L21/26586 , H01L21/823412 , H01L27/088 , H01L27/10894 , H01L27/10897
摘要： A semiconductor device includes a memory cell, a bit line coupled to the memory cell, first and second wells arranged adjacently to each other, the first and second wells being different in conductivity type from each other and defining a boundary therebetween, first and second transistors formed in the first and second wells, respectively, and being different in channel type from each other, gate electrodes of the first and second transistors being connected in common to the bit line, and a third transistor formed in the first well such that the third transistor is sandwiched between the boundary and the first transistor, and a gate of the third transistor being supplied with a bit line precharge signal.
摘要翻译：半导体器件包括存储单元，耦合到存储单元的位线，彼此相邻布置的第一和第二阱，第一和第二阱彼此不同，导电类型彼此不同，并且在其间界定第一和第二晶体管分别形成在第一和第二阱中，并且沟道类型彼此不同，第一和第二晶体管的栅电极共同连接到位线，并且第三晶体管形成在第一阱中，使得第三阱晶体管夹在边界和第一晶体管之间，并且第三晶体管的栅极被提供有位线预充电信号。

4. 发明授权

US08102726B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08102726B2
公开(公告)日：2012-01-24
申请号：US12318417
申请日：2008-12-29
申请人： Yasuhiro Matsumoto , Yasuji Koshikawa
发明人： Yasuhiro Matsumoto , Yasuji Koshikawa
IPC分类号： G11C7/02
CPC分类号： H01L27/0207 , H01L21/26586 , H01L21/823412 , H01L27/088 , H01L27/10894 , H01L27/10897
摘要： A semiconductor device includes a plurality of memory cells and a sense amplifier circuit which further includes a plurality of elements such as MOS transistor formed in a well, wherein sensitive element, which are sensitive to dispersion of an impurity density in the well, is distanced from a boundary and are disposed in the center region of the well, while non-sensitive element is disposed in the peripheral region close to the boundary in the well. Since sensitive element requiring precise control of threshold voltage is disposed in the center region having uniform impurity density, and non-sensitive element allowing for less precise control of threshold voltage is disposed in the peripheral region suffering from uneven impurity density, it is possible to effectively use the overall area of the well and to thereby suppress an increase in the layout area of chips.
摘要翻译：半导体器件包括多个存储单元和读出放大器电路，其还包括形成在阱中的诸如MOS晶体管的多个元件，其中对井中的杂质密度的分散敏感的敏感元件远离并且设置在井的中心区域中，而非敏感元件设置在靠近井中边界的周边区域中。由于需要精确控制阈值电压的敏感元件被布置在具有均匀杂质浓度的中心区域中，并且允许不精确控制阈值电压的非敏感元件设置在具有不均匀杂质浓度的周边区域中，因此可以有效地使用井的整体面积，从而抑制芯片的布局面积的增加。

5. 发明申请

US20100124134A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20100124134A1
公开(公告)日：2010-05-20
申请号：US12318417
申请日：2008-12-29
申请人： Yasuhiro Matsumoto , Yasuji Koshikawa
发明人： Yasuhiro Matsumoto , Yasuji Koshikawa
IPC分类号： G11C7/00 , H01L29/66 , G11C7/06
CPC分类号： H01L27/0207 , H01L21/26586 , H01L21/823412 , H01L27/088 , H01L27/10894 , H01L27/10897
摘要： A semiconductor device includes a plurality of memory cells and a sense amplifier circuit which further includes a plurality of elements such as MOS transistor formed in a well, wherein sensitive element, which are sensitive to dispersion of an impurity density in the well, is distanced from a boundary and are disposed in the center region of the well, while non-sensitive element is disposed in the peripheral region close to the boundary in the well. Since sensitive element requiring precise control of threshold voltage is disposed in the center region having uniform impurity density, and non-sensitive element allowing for less precise control of threshold voltage is disposed in the peripheral region suffering from uneven impurity density, it is possible to effectively use the overall area of the well and to thereby suppress an increase in the layout area of chips.
摘要翻译：半导体器件包括多个存储单元和读出放大器电路，其还包括形成在阱中的诸如MOS晶体管的多个元件，其中对井中的杂质密度的分散敏感的敏感元件远离并且设置在井的中心区域中，而非敏感元件设置在靠近井中边界的周边区域中。由于需要精确控制阈值电压的敏感元件被布置在具有均匀杂质浓度的中心区域中，并且允许不精确控制阈值电压的非敏感元件设置在具有不均匀杂质浓度的周边区域中，因此可以有效地使用井的整体面积，从而抑制芯片的布局面积的增加。

6. 发明授权

US07652904B2 Semiconductor memory device having plural memory cell arrays 有权
标题翻译：具有多个存储单元阵列的半导体存储器件
公开(公告)号：US07652904B2
公开(公告)日：2010-01-26
申请号：US11956448
申请日：2007-12-14
申请人： Chiaki Dono , Yasuji Koshikawa , Jun Suzuki
发明人： Chiaki Dono , Yasuji Koshikawa , Jun Suzuki
IPC分类号： G11C5/02
CPC分类号： G11C5/02 , G11C5/06
摘要： A semiconductor memory device includes first and second bus regions, a third bus region laid out along a center line, a first cell region laid out between a first side and the first bus region, a second cell region laid out between a second side and the second bus region, third and fourth cell regions laid out between the first and second bus regions and laid out toward a third side and a fourth side respectively seen from the third bus region, and a data input/output pad string laid out along the third bus region.
摘要翻译：半导体存储器件包括第一和第二总线区域，沿着中心线布置的第三总线区域，布置在第一侧面与第一总线区域之间的第一单元区域，布置在第二侧面与第二区域之间的第二单元区域，第二总线区域，第三和第四单元区域，布置在第一和第二总线区域之间并且分别朝向从第三总线区域看到的第三侧面和第四侧面布置，以及沿着第三总线区域布置的数据输入/输出焊盘串巴士区。

7. 发明申请

US20080144346A1 SEMICONDUCTOR MEMORY DEVICE HAVING PLURAL MEMORY CELL ARRAYS 有权
标题翻译：具有多个存储器单元阵列的半导体存储器件
公开(公告)号：US20080144346A1
公开(公告)日：2008-06-19
申请号：US11956448
申请日：2007-12-14
申请人： Chiaki Dono , Yasuji Koshikawa , Jun Suzuki
发明人： Chiaki Dono , Yasuji Koshikawa , Jun Suzuki
IPC分类号： G11C5/02
CPC分类号： G11C5/02 , G11C5/06
摘要： A semiconductor memory device includes first and second bus regions, a third bus region laid out along a center line, a first cell region laid out between a first side and the first bus region, a second cell region laid out between a second side and the second bus region, third and fourth cell regions laid out between the first and second bus regions and laid out toward a third side and a fourth side respectively seen from the third bus region, and a data input/output pad string laid out along the third bus region.
摘要翻译：半导体存储器件包括第一和第二总线区域，沿着中心线布置的第三总线区域，布置在第一侧面与第一总线区域之间的第一单元区域，布置在第二侧面与第二区域之间的第二单元区域，第二总线区域，第三和第四单元区域，布置在第一和第二总线区域之间并且分别朝向从第三总线区域看到的第三侧面和第四侧面布置，以及沿着第三总线区域布置的数据输入/输出焊盘串巴士区。

8. 发明授权

US07742356B2 Semiconductor memory device having a refresh cycle changing circuit 有权
标题翻译：具有刷新周期改变电路的半导体存储器件
公开(公告)号：US07742356B2
公开(公告)日：2010-06-22
申请号：US11987767
申请日：2007-12-04
申请人： Chiaki Dono , Yasuji Koshikawa
发明人： Chiaki Dono , Yasuji Koshikawa
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/40611 , G11C11/40615
摘要： A semiconductor memory device includes a first refresh cycle changing circuit that changes a refresh cycle according to an auto-refresh mode, without giving influence to a refresh cycle according to a self-refresh mode, and a second refresh cycle changing circuit that changes a refresh cycle according to the self-refresh mode, without giving influence to a refresh cycle according to the auto-refresh mode. In this way, according to the present invention, the refresh cycle according to the auto-refresh mode and the refresh cycle according to the self-refresh mode can be controlled independently. Therefore, refresh operation considering the characteristic of each mode can be executed.
摘要翻译：半导体存储器件包括：第一刷新周期改变电路，其根据自刷新模式改变刷新周期，而不影响根据自刷新模式的刷新周期;以及第二刷新周期改变电路，其改变刷新根据自刷新模式循环，而不会根据自动刷新模式对刷新周期产生影响。以这种方式，根据本发明，可以独立地控制根据自刷新模式的刷新周期和根据自刷新模式的刷新周期。因此，可以执行考虑每个模式的特性的刷新操作。

9. 发明申请

US20070242546A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20070242546A1
公开(公告)日：2007-10-18
申请号：US11736421
申请日：2007-04-17
申请人： Yasuji Koshikawa
发明人： Yasuji Koshikawa
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/40611 , G11C11/40622 , G11C2211/4061
摘要： A semiconductor memory device is comprised of a refresh counter for sequentially generating a count value indicating one or more row addresses corresponding to one or more word lines to be refreshed when receiving a refresh request at a predetermined interval in normal operation, in which the refresh counter includes n+1 stage counters assigned to n bits included in the row address and a dummy bit not included in the row address, and a counter portion from the least significant bit to the dummy bit forms an N-ary counter, so as to control whether or not refresh is performed in response to a value of the dummy bit when receiving the refresh request.
摘要翻译：半导体存储器件包括刷新计数器，用于当在正常操作中以预定间隔接收到刷新请求时，顺序产生指示要刷新的一个或多个字线对应的一个或多个行地址的计数值，其中刷新计数器分配给包括在行地址中的n位的n + 1级计数器和不包括在行地址中的伪位，并且从最低有效位到虚拟位的计数器部分形成N进制计数器，以便控制是否在接收刷新请求时响应于虚拟位的值来执行刷新。

10. 发明授权

US06175534B1 Synchronous semiconductor storage device 有权
标题翻译：同步半导体存储装置
公开(公告)号：US06175534B1
公开(公告)日：2001-01-16
申请号：US09299839
申请日：1999-04-26
申请人： Junya Taniguchi , Yasuji Koshikawa , Kouji Mine
发明人： Junya Taniguchi , Yasuji Koshikawa , Kouji Mine
IPC分类号： G11C800
CPC分类号： G01R31/31701
摘要： According to one disclosed embodiment, a synchronous semiconductor storage device (100) includes a circuit for accomplishing mode setting operations after a test mode is entered, where the test mode includes a higher frequency internal clock. A synchronous semiconductor storage device (100) generates a first internal synchronous clock signal ICLK which can be used to enter mode setting values to a mode register setting circuit (122). At the same time, an external synchronous signal CSB can be applied to generate a second internal synchronous clock signal CSCLK. The ICLK and CSCLK values can be used to generate a higher frequency clock ICLK′ in a test mode. The ICLK′ signal can be applied to internal circuits (124) allowing such circuits to operate at a higher speed. The ICLK′ signal is not applied to the mode register setting circuit (122), thereby avoiding the possible latching of incorrect mode setting values by the mode register setting circuit (122).
摘要翻译：根据一个公开的实施例，同步半导体存储装置（100）包括用于在进入测试模式之后完成模式设置操作的电路，其中测试模式包括较高频率的内部时钟。同步半导体存储装置（100）产生可以用于将模式设定值输入到模式寄存器设定电路（122）的第一内部同步时钟信号ICLK。同时，可以施加外部同步信号CSB以产生第二内部同步时钟信号CSCLK。 ICLK和CSCLK值可用于在测试模式下生成更高频率的时钟ICLK'。 ICLK信号可以应用于内部电路（124），允许这种电路以更高的速度运行。 ICLK信号不被施加到模式寄存器设置电路（122），从而避免模式寄存器设置电路（122）可能锁定不正确的模式设置值。

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