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1. 发明申请

US20080313487A1 PROCESSING DEVICE AND CLOCK CONTROL METHOD 失效
标题翻译：处理装置和时钟控制方法
公开(公告)号：US20080313487A1
公开(公告)日：2008-12-18
申请号：US12136988
申请日：2008-06-11
申请人： Yoshinori MOCHIZUKI , Masaharu Ukeda , Shigemasa Shiota
发明人： Yoshinori MOCHIZUKI , Masaharu Ukeda , Shigemasa Shiota
IPC分类号： G06F1/08
CPC分类号： G06F1/24 , G06F1/04
摘要： A processing device comprises an interface and its control circuit for performing data transfer in synchronization with an external clock, an internal oscillator, and an interface and its control circuit for performing data transfer by using an internal clock generated by the internal oscillator. In the processing device, a clock control circuit that switches a system clock between the internal clock and the external clock in accordance with the interface is provided. When the system clock is switched, the switching is performed after the CPU is set in a sleep state, and after the switching is completed, the sleep state of the CPU is released to restart the operation.
摘要翻译：处理装置包括与外部时钟同步的数据传送接口及其控制电路，内部振荡器和接口及其控制电路，用于通过内部振荡器产生的内部时钟进行数据传输。在处理装置中，提供了根据接口在内部时钟和外部时钟之间切换系统时钟的时钟控制电路。当系统时钟切换时，在CPU设置为休眠状态之后进行切换，在切换完成后，释放CPU的休眠状态以重启动作。

2. 发明申请

US20100034024A1 Control Method For Nonvolatile Memory and Semiconductor Device 有权
标题翻译：非易失性存储器和半导体器件的控制方法
公开(公告)号：US20100034024A1
公开(公告)日：2010-02-11
申请号：US12494817
申请日：2009-06-30
申请人： Yoshinori MOCHIZUKI , Masaharu Ukeda , Shigemasa Shiota
发明人： Yoshinori MOCHIZUKI , Masaharu Ukeda , Shigemasa Shiota
IPC分类号： G11C7/00 , G06F12/00
CPC分类号： G11C16/10 , G11C16/105
摘要： In a nonvolatile memory, the threshold is restored to a state before changing, without increasing number of writing undesirably. In a system including a nonvolatile memory, a random number generator, and a controller accessible to the nonvolatile memory, every time access to the nonvolatile memory is performed, the controller determines a refresh-targeted area, based on a random number generated by the random number generator. The controller is made to perform refresh control to re-write to the refresh-targeted area. By such refresh control, the threshold is restored to a state before changing, without increasing the number of writing undesirably.
摘要翻译：在非易失性存储器中，阈值恢复到改变之前的状态，而不增加写入次数。在包括非易失性存储器，随机数发生器和非易失性存储器可访问的控制器的系统中，每次执行对非易失性存储器的访问时，控制器基于随机数产生的随机数来确定刷新目标区域数字发生器。使控制器执行刷新控制以重新写入刷新目标区域。通过这种刷新控制，阈值恢复到改变之前的状态，而不增加写入次数。

3. 发明申请

US20090144834A1 DATA PROCESSING CIRCUIT AND COMMUNICATION MOBILE TERMINAL DEVICE 审中-公开
标题翻译：数据处理电路和通信移动终端设备
公开(公告)号：US20090144834A1
公开(公告)日：2009-06-04
申请号：US12271099
申请日：2008-11-14
申请人： Yoshinori MOCHIZUKI , Masaharu Ukeda , Shigemasa Shiota , Takeo Kon
发明人： Yoshinori MOCHIZUKI , Masaharu Ukeda , Shigemasa Shiota , Takeo Kon
IPC分类号： H04L9/32 , H04M1/00 , G06F12/02
CPC分类号： G11C16/22 , G11C16/225
摘要： A data processing circuit includes a rewritable nonvolatile memory and a controller performing nonvolatile memory control and external interface control. A first detector and a second detector are employed to detect respectively whether the operation of the data processing circuit deviates from a first operating condition and a second operating condition, wherein the second operating condition is severer than the first operating condition. When the first detector detects deviation from the first operating condition, reset is instructed to the controller. When the second detector detects deviation from the second operating condition, the controller backs up an internal state and imposes a restriction on external access to a storage region of the nonvolatile memory. Accordingly, when operation of the microcontroller deviates from specific operating conditions within an operation guarantee range and performance degradation is exhibited, an unauthorized access to the data inside the microcontroller can be suppressed.
摘要翻译：数据处理电路包括可重写非易失性存储器和执行非易失性存储器控制和外部接口控制的控制器。采用第一检测器和第二检测器来检测数据处理电路的操作是否偏离第一操作条件和第二操作条件，其中第二操作条件比第一操作条件更严格。当第一检测器检测到与第一操作条件的偏差时，向控制器指示复位。当第二检测器检测到与第二操作条件的偏差时，控制器备份内部状态并对对非易失性存储器的存储区域的外部访问施加限制。因此，当微控制器的操作在操作保证范围内偏离特定操作条件并且表现出性能下降时，可以抑制对微控制器内的数据的未经授权的访问。

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