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1. 发明授权

US4701777A Gate array type semiconductor integrated circuit device 失效
标题翻译：门阵列型半导体集成电路器件
公开(公告)号：US4701777A
公开(公告)日：1987-10-20
申请号：US948406
申请日：1986-12-30
申请人： Yoshihisa Takayama , Shigeru Fujii , Tomoaki Tanabe
发明人： Yoshihisa Takayama , Shigeru Fujii , Tomoaki Tanabe
IPC分类号： H01L27/08 , H01L21/82 , H01L21/8234 , H01L27/088 , H01L27/092 , H01L27/118 , H01L27/02 , G11C5/02 , H01L27/10 , H01L27/15
CPC分类号： H01L27/0921 , H01L21/82 , H01L27/11807
摘要： A gate array type semiconductor device including at least a plurality of basic cell arrays and diffusion regions for suppressing latchup in the basic cells forming the basic cell arrays. Each of the diffusion regions has a comb-shaped structure, i.e., wide tooth parts, narrow tooth parts, and a base part, formed as an integral structure. These parts partially surround each basic cell.
摘要翻译：一种栅极阵列型半导体器件，包括至少多个基本单元阵列和用于抑制形成基本单元阵列的基本单元中的锁存的扩散区域。每个扩散区具有梳状结构，即形成为整体结构的宽齿部，窄齿部和基部。这些部分部分围绕每个基本单元。

2. 发明授权

US4780846A Master slice type semiconductor circuit device 失效
标题翻译：主片式半导体电路器件
公开(公告)号：US4780846A
公开(公告)日：1988-10-25
申请号：US750163
申请日：1985-06-28
申请人： Tomoaki Tanabe , Shigeru Fujii , Yoshihisa Takayama
发明人： Tomoaki Tanabe , Shigeru Fujii , Yoshihisa Takayama
IPC分类号： G11C5/02 , G11C5/06 , G11C5/14 , G11C8/00 , H01L23/528 , H01L27/118 , H03K17/687
CPC分类号： G11C8/00 , G11C5/025 , G11C5/063 , G11C5/14 , H01L23/528 , H01L27/11807 , H03K17/6872 , H01L2027/11838 , H01L2924/0002
摘要： A master slice type semiconductor circuit device including a memory block having at least one memory circuit; one conductive layer provided to peripheral portions of the memory circuit and used as an input portion thereto; power source lines provided to the peripheral portion of the memory circuit and formed by a conductive layer different from the conductive layer of the input portion; and a contact hole for connecting between the two conductive layers at a selected input portion. The selected input portion connected by the contact hole is set or clamped to a predetermined logic level by the power source line. This enables a change of the memory capacity or the function of the memory block to satisfy customer requirements.
摘要翻译：一种主切片型半导体电路装置，包括具有至少一个存储电路的存储块; 提供给存储电路的周边部分并用作其输入部分的一个导电层; 电源线提供到存储电路的周边部分，并由与输入部分的导电层不同的导电层形成; 以及用于在所选择的输入部分处连接两个导电层之间的接触孔。通过接触孔连接的所选择的输入部分被电源线设置或钳位到预定的逻辑电平。这样可以改变内存容量或内存块的功能，以满足客户的要求。

3. 发明授权

US5132563A LSI gate array having reduced switching noise 失效
标题翻译：具有降低开关噪音的LSI门阵列
公开(公告)号：US5132563A
公开(公告)日：1992-07-21
申请号：US746158
申请日：1991-08-14
申请人： Shigeru Fujii , Kouichi Yamashita , Tomoaki Tanabe , Yoshio Kuniyasu
发明人： Shigeru Fujii , Kouichi Yamashita , Tomoaki Tanabe , Yoshio Kuniyasu
IPC分类号： H01L21/8234 , H01L21/82 , H01L27/088 , H01L27/118 , H03K19/003 , H03K19/08
CPC分类号： H03K19/00361 , H01L27/11807
摘要： As the number of output circuits in LSI or VLSI circuits increases, the chance of many large output circuits operating as a same instant increases, which can cause a malfunction in the logic due to induced switching noise. In order to prevent such a problem, the switching speed of the driving buffer circuit for an output buffer circuit is controlled. By reducing the switching capacity of the driving circuit, the switching speed of the total circuit is not greatly affected and the noise is greatly decreased. Control of the switching capacity of the driving buffer circuit is performed by master slice technology. This opposite design concept, compared to that of prior art LSI design, has been proved by experiments.

4. 发明授权

US4661815A Gate array integrated device having mixed single column type and matrix type arrays 失效
标题翻译：门阵列集成器件具有混合单列型和矩阵型阵列
公开(公告)号：US4661815A
公开(公告)日：1987-04-28
申请号：US782923
申请日：1985-10-02
申请人： Yoshihisa Takayama , Shigeru Fujii , Kazuyuki Kawauchi , Toshihiko Yoshida
发明人： Yoshihisa Takayama , Shigeru Fujii , Kazuyuki Kawauchi , Toshihiko Yoshida
IPC分类号： H01L27/04 , H01L23/528 , H01L27/02 , H01L27/092 , H01L27/118 , H04Q1/00 , H01L29/78 , H03K19/177
CPC分类号： H01L27/092 , H01L23/528 , H01L27/0218 , H01L27/11807 , H01L2924/0002 , H01L2924/3011
摘要： A gate array integrated device including a plurality of single column type arrays, a plurality of matrix type arrays such as double column type arrays (BC2), and longitudinal connection areas (CH) provided between the single column type arrays and the matrix type arrays. One of the single column type arrays facing at least one side of each of the matrix type arrays.
摘要翻译：一种门阵列集成器件，包括多个单列型阵列，多列矩阵型阵列，例如双列阵列阵列（BC2）和纵列连接区域（CH），其设置在单列阵列和阵列阵列之间。单列式阵列中的一个面向每个矩阵型阵列的至少一侧。

5. 发明授权

US4727266A LSI gate array having reduced switching noise 失效
标题翻译： LSI门阵列具有降低的开关噪声
公开(公告)号：US4727266A
公开(公告)日：1988-02-23
申请号：US18846
申请日：1987-02-24
申请人： Shigeru Fujii , Kouichi Yamashita , Tomoaki Tanabe , Yoshio Kuniyasu
发明人： Shigeru Fujii , Kouichi Yamashita , Tomoaki Tanabe , Yoshio Kuniyasu
IPC分类号： H01L21/8234 , H01L21/82 , H01L27/088 , H01L27/118 , H03K19/003 , H03K19/08 , H03K17/16
CPC分类号： H03K19/00361 , H01L27/11807
摘要： As the number of output circuit increases in LSI or VLSI circuit, there increases the chance of many large output circuits operates at a same instant, and it causes malfunction of logic by induced switching noise. In order to prevent such problem, the switching speed of driving buffer circuit for output buffer circuit is controlled. By reducing the switching capacity of the driving circuit, the switching speed of the total circuit is not affected so much, but the noise is decreased very much. The control of the switching capacity of the driving buffer circuit is performed by master slice technology. Such as perfectly opposite design concept to that of present LSI design has been proofed by experiments.
摘要翻译：随着LSI或VLSI电路中输出电路的数量增加，许多大输出电路在同一时刻运行的可能性增加，并且通过感应开关噪声导致逻辑故障。为了防止这种问题，控制用于输出缓冲电路的驱动缓冲电路的切换速度。通过降低驱动电路的开关容量，总电路的开关速度不会受到很大的影响，但是噪声降低很多。驱动缓冲电路的开关容量的控制由主切片技术进行。像现在的LSI设计完全相反的设计理念已经通过实验证明了。

6. 发明授权

US5731687A Generator assembly 失效
标题翻译：发电机总成
公开(公告)号：US5731687A
公开(公告)日：1998-03-24
申请号：US634277
申请日：1996-04-18
申请人： Tutomu Hirano , Shigeru Fujii , Masashi Nakamura
发明人： Tutomu Hirano , Shigeru Fujii , Masashi Nakamura
IPC分类号： F02B63/04 , F02B77/13 , H02K5/04
CPC分类号： F02B63/04 , F02B77/13 , F02B2063/045 , F02B63/044
摘要： In a generator assembly, outside air, taken from a suction hole into a fixed soundproof housing, is sucked into a portable engine generator covered by a soundproof case to operate an engine and cool the interior of the fixed soundproof housing. The exhaust gas of the engine and the cooling air of the soundproof case are exhausted outside through the exhaust air hole of the soundproof case and the external exhaust hole of the fixed soundproof housing without leaking into the fixed soundproof housing. Therefore, the portable engine generator can be operated while it remains housed within the fixed soundproof housing. The exhaust air duct of the portable engine generator and the communicating duct of the fixed soundproof housing are communicated in a state of close contact, at the time that the portable engine generator has been positioned by a positioning member provided in the fixed soundproof housing. The portable engine generator can be put into or out from the fixed soundproof housing and is guided and housed by wheel guide rails provided within the fixed soundproof housing.
摘要翻译：在发电机组件中，从抽吸孔取入固定隔音壳体的外部空气被吸入由隔音壳体覆盖的便携式发动机发电机中，以操作发动机并且冷却固定隔音壳体的内部。发动机的排气和隔音箱的冷却空气通过隔音壳体的排气孔和固定隔音壳体的外部排气孔排出外部，而不会泄漏到固定隔音壳体中。因此，便携式发动机发电机可以在其保持在固定隔音壳体内时被操作。便携式发动机发电机的排气风道和固定隔音壳体的连通管道在通过设置在固定隔音壳体中的定位构件定位的状态下以紧密接触的状态通信。便携式发电机可以从固定隔音壳体放入或导出，并由设在固定隔音壳体内的轮子导轨引导和收纳。

7. 发明授权

US5093611A Output circuit for portable generators 失效
标题翻译：便携式发电机的输出电路
公开(公告)号：US5093611A
公开(公告)日：1992-03-03
申请号：US554194
申请日：1990-07-17
申请人： Masashi Nakamura , Shigeru Fujii
发明人： Masashi Nakamura , Shigeru Fujii
IPC分类号： B23K9/10
CPC分类号： B23K9/10 , Y10T307/289
摘要： An output circuit for a portable generator having a plurality of output windings provided separately from each other, and control winding provided separately from the output windings. A plurality of thyristor bridge circuits each having thyristors are connected respectively to the output windings. A superposing circuit superposes outputs from the thyristor bridge circuits one upon another to provide a first superposed output voltage. A rectifier circuit is connected to the control winding. The rectifier circuit is disposed such that its output voltage is superposed upon the first superposed output voltage to provide a second superposed output voltage. A control circuit is responsive to the second superposed output voltage for concurrently controlling voltages applied respectively to the gates of the thyristors of the thyristor bridge circuits to thereby maintain the first superposed output voltage at a constant value. An FET is connected to the output of the superposing circuit, and is connectible in series to an external load, for controlling supply of current flowing through the FET to the external load. A current cut-off circuit detects overcurrent in the output circuit and operable, upon detection of the overcurrent, to cause the FET to be turned off to thereby cut off the supply of current to the external load.
摘要翻译：一种用于便携式发电机的输出电路，具有彼此分开设置的多个输出绕组，以及与输出绕组分开设置的控制绕组。各自具有晶闸管的多个晶闸管桥接电路分别连接到输出绕组。叠加电路将晶闸管桥接电路的输出叠加起来以提供第一叠加输出电压。整流电路连接到控制绕组。整流电路被布置成使得其输出电压叠加在第一叠加输出电压上以提供第二叠加输出电压。控制电路响应于第二重叠输出电压，以同时控制分别施加到晶闸管桥接电路的晶闸管的栅极的电压，从而将第一叠加输出电压保持在恒定值。 FET连接到叠加电路的输出端，可与外部负载串联连接，用于控制流过FET至外部负载的电流供应。电流截止电路检测输出电路中的过电流，并且在检测到过电流时可操作，以使FET截止，从而切断对外部负载的电流供应。

8. 发明授权

US3963803A Antistatic acrylic fiber 失效
标题翻译：防静电丙烯酸纤维
公开(公告)号：US3963803A
公开(公告)日：1976-06-15
申请号：US400207
申请日：1973-09-24
申请人： Hiroyoshi Tanaka , Haruo Obara , Teruo Koseki , Hajime Machida , Michihiko Tanaka , Shigeru Fujii
发明人： Hiroyoshi Tanaka , Haruo Obara , Teruo Koseki , Hajime Machida , Michihiko Tanaka , Shigeru Fujii
IPC分类号： C08L33/18 , C08L67/02 , D01F6/54 , C08G39/10
CPC分类号： D01F6/54 , C08L33/18 , C08L67/025 , Y10S260/17
摘要： An acrylic fiber having excellent antistatic properties is obtained by mixing a polymer (A) consisting mainly of acrylonitrile with a copolymer (B) consisting mainly of a polyetherpolyester block copolymer consisting of a polyester and compound represented by the general formula (1): ##EQU1## (wherein each of m and n is O or a positive integer, wherein 25 .ltoreq. m + n .ltoreq. 1000, and m .gtoreq. 10).
摘要翻译：通过将主要由丙烯腈组成的聚合物（A）与主要由聚酯和由通式（1）表示的化合物组成的聚醚聚酯嵌段共聚物共聚物（B））混合得到具有优异抗静电性能的丙烯酸纤维：CH3 | HO-CH 2 CH 2 O）m - （CH 2 CH.OnH（1）（其中m和n分别为O或正整数，其中25≤m+ n <1000，m> = 10）。

9. 外观设计

USD645367S1 Automated analyzer 有权
标题翻译：自动分析仪
公开(公告)号：USD645367S1
公开(公告)日：2011-09-20
申请号：US29376231
申请日：2010-10-04
申请人： Yoshihiro Hayashi , Shigeru Fujii
设计人： Yoshihiro Hayashi , Shigeru Fujii

10. 发明申请

US20080227226A1 Semiconductor substrate, manufacturing method of a semiconductor device and testing method of a semiconductor device 审中-公开
标题翻译：半导体衬底，半导体器件的制造方法和半导体器件的测试方法
公开(公告)号：US20080227226A1
公开(公告)日：2008-09-18
申请号：US12153481
申请日：2008-05-20
申请人： Shigeru Fujii , Yoshikazu Arisaka , Hitoshi Izuru , Kazuhiro Tashiro , Shigeyuki Maruyama
发明人： Shigeru Fujii , Yoshikazu Arisaka , Hitoshi Izuru , Kazuhiro Tashiro , Shigeyuki Maruyama
IPC分类号： H01L21/66 , H01L21/304
CPC分类号： H01L21/78 , H01L23/544 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor substrate eliminates a restriction caused by a width of scribe lines so as to increase a number of semiconductor elements formed on the semiconductor substrate. A plurality of semiconductor element areas are formed by forming a plurality of unit exposed and printed areas, each of which contains the semiconductor element areas. A first scribe line extends between the semiconductor element areas formed within the unit exposed and printed area. A second scribe line extends between the unit exposed and printed areas. A width of the first scribe line is different from a width of the second scribe line.
摘要翻译：半导体衬底消除了由划线的宽度引起的限制，从而增加形成在半导体衬底上的半导体元件的数量。多个半导体元件区域通过形成多个单位曝光和印刷区域而形成，每个单元暴露和印刷区域都包含半导体元件区域。第一刻划线在形成在单元曝光和印刷区域内的半导体元件区域之间延伸。第二划线在单元曝光和打印区域之间延伸。第一划线的宽度与第二划线的宽度不同。

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