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1. 发明授权

US4954871A Semiconductor device with composite electrode 失效
标题翻译：具有复合电极的半导体器件
公开(公告)号：US4954871A
公开(公告)日：1990-09-04
申请号：US147107
申请日：1988-01-21
申请人： Yoshihisa Mizutani , Minoru Kimura
发明人： Yoshihisa Mizutani , Minoru Kimura
IPC分类号： H01L21/8238 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/532 , H01L27/092 , H01L29/49 , H01L29/78
CPC分类号： H01L29/4916 , H01L21/76889 , H01L23/53271 , H01L27/0927 , H01L29/78 , H01L2924/0002
摘要： Provided is a semiconductor device having a single continuous wiring layer in which a predetermined portion thereof is made of a semiconductor material, and the remaining portion thereof is made of a metal compound of the semiconductor material. The predetermined portion of the wiring layer preferably constitutes the gate electrode of a field effect transistor.
摘要翻译：提供了具有单个连续布线层的半导体器件，其中预定部分由半导体材料制成，其余部分由半导体材料的金属化合物制成。布线层的预定部分优选构成场效应晶体管的栅电极。

2. 发明授权

US4882707A Non-volatile semi-conductor memory device with double gate structure 失效
标题翻译：具有双栅极结构的非易失性半导体存储器件
公开(公告)号：US4882707A
公开(公告)日：1989-11-21
申请号：US316534
申请日：1989-02-27
申请人： Yoshihisa Mizutani
发明人： Yoshihisa Mizutani
IPC分类号： G11C16/04 , H01L27/115 , H01L29/08 , H01L29/78 , H01L29/788
CPC分类号： H01L29/7885 , G11C16/0416 , H01L27/115 , H01L29/0847 , H01L29/7839
摘要： A memory cell structure for a non-volatile semiconductor memory has a semiconductor substrate and first and second diffusion layers having a conductivity type opposite to that of the substrate, formed on the substrate and serve as a source and a drain. The second diffusion layer is coupled through a contact hole to a conductive layer that serves as a bit line. The functions of the first and second diffusion layers as the source and drain are reversed between data write and read modes. A floating gate and a control gate are insulatively provided on the substrate in parallel to each other. In either the data write mode or data read mode, the first and second diffusion layer are applied with a bias voltage while the control gate is initially applied with a ground voltage. A memory cell is selected by dropping the bias voltage on the second diffusion layer. The potential on the first diffusion layer is kept unchanged to constantly maintain the initially-applied bias voltage even when the memory cell is selected, so that the first diffusion layer is permitted to be coupled to the common wiring line together with the corresponding first diffusion layers of the other memory cells.
摘要翻译：用于非易失性半导体存储器的存储单元结构具有半导体衬底和形成在衬底上并用作源极和漏极的具有与衬底相反的导电类型的第一和第二扩散层。第二扩散层通过接触孔耦合到用作位线的导电层。作为源极和漏极的第一和第二扩散层的功能在数据写入和读取模式之间相反。浮动栅极和控制栅极彼此平行地绝缘地设置在基板上。在数据写入模式或数据读取模式中，在控制栅极初始施加接地电压的同时，施加偏置电压的第一和第二扩散层。通过将偏压降到第二扩散层来选择存储单元。即使选择了存储单元，第一扩散层上的电位保持不变，以始终保持初始施加的偏置电压，使得第一扩散层与相应的第一扩散层一起被允许耦合到公共布线的其他存储单元。

3. 发明授权

US4878199A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US4878199A
公开(公告)日：1989-10-31
申请号：US150052
申请日：1988-01-29
申请人： Yoshihisa Mizutani
发明人： Yoshihisa Mizutani
IPC分类号： H01L21/8247 , G11C16/10 , G11C16/22 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/115 , G11C16/10 , G11C16/22
摘要： An electrically erasable-programmable read-only memory device has memory cells formed on a semiconductive substrate. Each memory cell has source and drain layers, and a floating gate electrode and a control gate electrode insulatively provided above the substrate. First and second well regions having a polarity opposite to that of the substrate are formed therein so that each well region contains one or a plurality of memory cells therein. When information stored in the memory cell or memory cells in the first well region is to be rewritten with new information in a partial data rewrite mode, a potential of the first well region is independently controlled so as to inhibit reading and writing of information in the memory cells in the first well region. A potential of the second well region is separately controlled so as to allow writing of the new information in the memory cells in the second well region. The new information is written in the memory cell or memory cells in the second well region. The written information can be subjected to a following normal data read operation. The memory cell or memory cells in the first well region become inactive thereafter.
摘要翻译：电可擦可编程只读存储器件具有形成在半导体衬底上的存储单元。每个存储单元具有源极和漏极层，以及绝缘地设置在衬底上方的浮置栅电极和控制栅电极。在其中形成具有与基板的极性相反的极性的第一和第二阱区，使得每个阱区在其中包含一个或多个存储单元。当以部分数据重写模式中的新信息重写存储在第一阱区中的存储单元或存储单元中的信息时，第一阱区的电位被独立地控制，以便抑制在第一阱区中的信息的读取和写入第一井区的记忆细胞。单独控制第二阱区的电位，以便允许将新信息写入第二阱区中的存储单元。新信息被写入第二阱区中的存储单元或存储单元。写入的信息可以进行以下正常的数据读取操作。第一阱区中的存储单元或存储单元在此之后变为无效。

4. 发明授权

US4754320A EEPROM with sidewall control gate 失效
标题翻译：带侧壁控制门的EEPROM
公开(公告)号：US4754320A
公开(公告)日：1988-06-28
申请号：US832580
申请日：1986-02-24
申请人： Yoshihisa Mizutani , Susumu Kohyama , Koji Makita
发明人： Yoshihisa Mizutani , Susumu Kohyama , Koji Makita
IPC分类号： H01L21/28 , H01L21/8247 , H01L29/788 , H01L29/78 , H01L29/44
CPC分类号： H01L27/11526 , H01L21/2815 , H01L21/28273 , H01L27/11517 , H01L27/11543 , H01L29/7885 , Y10S257/90
摘要： A semiconductor device, and more particularly, an erasable programmable read only memory has a control gate electrode and a floating gate electrode. The floating gate electrode is formed on one side wall of the control gate electrode through an insulating film.
摘要翻译：更具体地，可擦除可编程只读存储器的半导体器件具有控制栅电极和浮栅电极。浮栅电极通过绝缘膜形成在控制栅电极的一个侧壁上。

5. 发明授权

US4637128A Method of producing semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US4637128A
公开(公告)日：1987-01-20
申请号：US726399
申请日：1985-04-23
申请人： Yoshihisa Mizutani
发明人： Yoshihisa Mizutani
IPC分类号： H01L29/78 , H01L21/265 , H01L21/76 , H01L21/762 , H01L21/8247 , H01L29/788 , H01L29/792 , H01L21/308
CPC分类号： H01L27/11517 , H01L21/2652 , H01L21/76216 , Y10S148/082 , Y10S148/085
摘要： A method of producing a semiconductor device comprises an isolation step for forming an n-type region in contact with p.sup.+ -type source and drain regions of a p-channel floating gate MOS transistor in the surface area of an n-type semiconductor substrate and an n.sup.+ -type region in contact with the n-type region. In this isolation step, and oxidation resistant film pattern is formed on the element region of the MOS transistor. An anisotropic etching is applied to the substrate with the oxidation resistant film pattern used as a mask to form an inclined portion and a flat portion, followed by forming a SiO.sub.2 film of a prescribed thickness to cover both the inclined and flat portions. Further, an n-type impurity is introduced by ion implantation into the substrate through the SiO.sub.2 film in a direction perpendicular to the flat portion, followed by annealing the ion-implanted region.
摘要翻译：一种制造半导体器件的方法包括：隔离步骤，用于形成与n型半导体衬底的表面区域中的p沟道浮置栅极MOS晶体管的p +型源极和漏极区域接触的n型区域;以及 n +型区域与n型区域接触。在该隔离工序中，在MOS晶体管的元件区域上形成耐氧化膜图案。用抗氧化膜图案作为掩模对基板施加各向异性蚀刻，以形成倾斜部分和平坦部分，然后形成规定厚度的SiO 2膜以覆盖倾斜部分和平坦部分。此外，通过离子注入将n型杂质通过SiO 2膜沿垂直于平坦部分的方向引入到衬底中，随后退火离子注入区域。

6. 发明授权

US4506279A Metal-oxide-semiconductor device with bilayered source and drain 失效
标题翻译：具有双层源极和漏极的金属氧化物半导体器件
公开(公告)号：US4506279A
公开(公告)日：1985-03-19
申请号：US531618
申请日：1983-09-13
申请人： Yoshihisa Mizutani
发明人： Yoshihisa Mizutani
IPC分类号： H01L29/78
CPC分类号： H01L29/78
摘要： A metal-oxide-semiconductor device comprising source and drain regions formed in the surface region of a semiconductor substrate, and a gate electrode formed on an insulation layer on the channel region between the source and drain regions. The drain region includes an upper layer and a lower layer having an impurity concentration higher than that of the upper layer.
摘要翻译：一种金属氧化物半导体器件，包括形成在半导体衬底的表面区域中的源极和漏极区域，以及形成在源极和漏极区域之间的沟道区域上的绝缘层上的栅电极。漏区包括杂质浓度高于上层的上层和下层。

7. 发明授权

US5172196A Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US5172196A
公开(公告)日：1992-12-15
申请号：US440427
申请日：1989-11-21
申请人： Naohiro Matsukawa , Yoshihisa Mizutani
发明人： Naohiro Matsukawa , Yoshihisa Mizutani
IPC分类号： G11C16/04 , H01L29/788
CPC分类号： G11C16/0416 , H01L29/7883
摘要： A nonvolatile semiconductor memory device has n.sup.+ -type source and drain regions formed in the surface of a p-type semiconductor substrate, a floating gate formed above and insulated from a channel region provided between the source and drain regions, and a control gate formed above and insulated from the floating gate. The memory device further has a capacitor provided between the control gate and drain region.
摘要翻译：非易失性半导体存储器件具有形成在p型半导体衬底的表面中的n +型源极和漏极区域，形成在源极和漏极区域之间的沟道区域上方并与绝缘区域形成的浮动栅极以及形成在上述并与浮动门隔绝。存储器件还具有设置在控制栅极和漏极区域之间的电容器。

8. 发明授权

US4661833A Electrically erasable and programmable read only memory 失效
标题翻译：电可擦除和可编程只读存储器
公开(公告)号：US4661833A
公开(公告)日：1987-04-28
申请号：US792562
申请日：1985-10-29
申请人： Yoshihisa Mizutani
发明人： Yoshihisa Mizutani
IPC分类号： H01L21/8234 , H01L21/8246 , H01L21/8247 , H01L27/088 , H01L27/10 , H01L27/112 , H01L27/115 , H01L29/788 , H01L29/792 , H01L29/78 , H01L27/02 , H01L29/06 , H01L29/34
CPC分类号： H01L27/11521 , H01L27/088 , H01L27/115
摘要： An electrically erasable and programmable read only memory comprises a semiconductor substrate of a first conductivity type, source and drain regions both of a second conductivity type formed in the surface of said semiconductor substrate, a gate insulation film formed on that section of the surface of said substrate which includes a channel region defined between said source and drain regions, a first diffusion region of the second conductivity type, part of which is formed in said substrate and contacts said drain region and which has a lower impurity concentration than said drain region, a first insulation film formed on said first diffusion region, a floating gate formed on said gate insulation film, part of which extends over said first insulation film, a second diffusion region of the first conductivity type formed in the surface of said first diffusion region which lies near said extension of the floating gate, a third diffusion region of the first conductivity type formed in the surface of said first diffusion region, a second insulation film covering said floating gate, and a control gate crossing at least that section of the surface of said second insulation layer which faces part of said floating gate.
摘要翻译：电可擦除可编程只读存储器包括第一导电类型的半导体衬底，形成在所述半导体衬底的表面中的第二导电类型的源极和漏极区域，形成在所述半导体衬底的表面的该部分上的栅极绝缘膜衬底，其包括限定在所述源极和漏极区域之间的沟道区域，第二导电类型的第一扩散区域，其一部分形成在所述衬底中并接触所述漏极区域并且具有比所述漏极区域低的杂质浓度，形成在所述第一扩散区上的第一绝缘膜，形成在所述栅绝缘膜上的浮栅，其一部分在所述第一绝缘膜上延伸，形成在所述第一扩散区的表面中的第一导电类型的第二扩散区，靠近浮动栅极的所述延伸部分，形成第一导电类型的第三扩散区域所述第一扩散区域的表面，覆盖所述浮动栅极的第二绝缘膜，以及至少与所述第二绝缘层的面对所述浮动栅极的一部分的部分交叉的控制栅极。

9. 发明授权

US4642880A Method for manufacturing a recessed semiconductor device 失效
标题翻译：凹陷半导体器件的制造方法
公开(公告)号：US4642880A
公开(公告)日：1987-02-17
申请号：US724152
申请日：1985-04-17
申请人： Yoshihisa Mizutani , Syunzi Yokogawa
发明人： Yoshihisa Mizutani , Syunzi Yokogawa
IPC分类号： H01L21/265 , H01L21/76 , H01L21/762 , H01L21/8234 , H01L21/8247 , H01L29/78 , H01L29/788 , H01L29/792 , H01L21/308
CPC分类号： H01L21/8234 , H01L21/76208 , H01L21/76216 , H01L29/7834 , H01L29/7885 , Y10S148/082 , Y10S148/085 , Y10S438/978
摘要： A method for manufacturing a semiconductor device comprises a first step of forming a field insulation layer on a p-type semiconductor substrate and a second step of forming an n.sup.+ -type region and n-type region in an element area surrounded by the field insulation layer. In particular, the second step includes a step of forming, in the element area, a recess having an inclined portion and flat bottom portion, a step of forming an SiO.sub.2 film of a uniform thickness on the inclined portion and flat bottom portion, and a step of ion-implanting an n-type impurity into the substrate through the SiO.sub.2 and effecting an annealing process.
摘要翻译：一种制造半导体器件的方法包括在p型半导体衬底上形成场绝缘层的第一步骤和在由场绝缘层包围的元件区域中形成n +型区域和n型区域的第二步骤。特别地，第二步骤包括在元件区域中形成具有倾斜部分和平坦底部部分的凹部的步骤，在倾斜部分和平坦底部部分上形成均匀厚度的SiO 2膜的步骤，以及通过SiO 2将n型杂质离子注入到衬底中并进行退火工艺。

10. 发明授权

US4479297A Method of fabricating three-dimensional semiconductor devices utilizing CeO.sub.2 and ion-implantation. 失效
标题翻译：使用CeO2和离子注入制造三维半导体器件的方法。
公开(公告)号：US4479297A
公开(公告)日：1984-10-30
申请号：US386808
申请日：1982-06-09
申请人： Yoshihisa Mizutani , Shinichiro Takasu
发明人： Yoshihisa Mizutani , Shinichiro Takasu
IPC分类号： H01L27/00 , H01L21/02 , H01L21/20 , H01L21/205 , H01L21/316 , H01L21/762 , H01L21/822 , H01L27/12 , H01L29/78 , H01L21/265
CPC分类号： H01L21/8221 , H01L21/31604 , H01L21/762 , H01L21/02381 , H01L21/0242 , H01L21/02488 , H01L21/02502 , H01L21/02521 , H01L21/02658 , Y10S438/967
摘要： A method for fabricating a three-dimensional multi-layer integrated circuit of single crystalline CeO.sub.2 and Si is proposed.This method is characterized in that a single crystalline CeO.sub.2 insulation layer, or the like, is formed on a single crystalline Si substrate. An isolation region is formed in the single crystalline Si substrate. The region is transformed into a SiO.sub.2 insulation layer by selectively introducing oxygen ions through the single crystalline CeO.sub.2 insulation layer and reacting the oxygen ions with the single crystalline Si.An epitaxial growth single crystalline Si layer is formed on the single crystalline CeO.sub.2 insulation layer.Predetermined processes, such as forming a single crystalline CeO.sub.2 layer, are performed thereafter to form the three-dimensional structures of semiconductor elements such as MOS transistors and bipolar transistors with high packing density and reliability.
摘要翻译：提出了一种制备单晶CeO2和Si三维多层集成电路的方法。该方法的特征在于，在单晶Si衬底上形成单晶CeO2绝缘层等。在单晶Si衬底中形成隔离区。通过选择性地将氧离子引入单晶CeO2绝缘层并使氧离子与单晶Si反应，将该区域转化为SiO 2绝缘层。在单晶CeO2绝缘层上形成外延生长单晶Si层。之后进行预定的工艺，例如形成单晶的CeO 2层，以形成具有高封装密度和可靠性的诸如MOS晶体管和双极晶体管的半导体元件的三维结构。

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