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1. 发明授权

US07995369B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07995369B2
公开(公告)日：2011-08-09
申请号：US12332595
申请日：2008-12-11
申请人： Yoshihiro Minami , Ryo Fukuda , Takeshi Hamamoto
发明人： Yoshihiro Minami , Ryo Fukuda , Takeshi Hamamoto
IPC分类号： G11C17/00
CPC分类号： H01L27/101 , H01L27/1021 , H01L27/112 , H01L27/1203
摘要： This disclosure concerns a semiconductor memory device including bit lines; word lines; semiconductor layers arranged to correspond to crosspoints of the bit lines and the word lines; bit line contacts connecting between a first surface region and the bit lines, the first surface region being a part of a surface region of the semiconductor layers directed to the word lines and the bit lines; and a word-line insulating film formed on a second surface region adjacent to the first surface region, the second surface region being a part of out of the surface region, the word-line insulating film electrically insulating the semiconductor layer and the word line, wherein the semiconductor layer, the word line and the word-line insulating film form a capacitor, and when a potential difference is given between the word line and the bit line, the word-line insulating film is broken in order to store data.
摘要翻译：本公开涉及包括位线的半导体存储器件; 字线布置成对应于位线和字线的交叉点的半导体层; 连接在第一表面区域和位线之间的位线触点，第一表面区域是半导体层指向字线和位线的表面区域的一部分; 以及形成在与所述第一表面区域相邻的第二表面区域上的字线绝缘膜，所述第二表面区域是所述表面区域之外的一部分，所述字线绝缘膜使所述半导体层和所述字线电绝缘，其中半导体层，字线和字线绝缘膜形成电容器，并且当在字线和位线之间给出电位差时，字线绝缘膜被破坏以便存储数据。

2. 发明申请

US20090152610A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20090152610A1
公开(公告)日：2009-06-18
申请号：US12332595
申请日：2008-12-11
申请人： Yoshihiro Minami , Ryo Fukuda , Takeshi Hamamoto
发明人： Yoshihiro Minami , Ryo Fukuda , Takeshi Hamamoto
IPC分类号： H01L29/78
CPC分类号： H01L27/101 , H01L27/1021 , H01L27/112 , H01L27/1203
摘要： This disclosure concerns a semiconductor memory device including bit lines; word lines; semiconductor layers arranged to correspond to crosspoints of the bit lines and the word lines; bit line contacts connecting between a first surface region and the bit lines, the first surface region being a part of a surface region of the semiconductor layers directed to the word lines and the bit lines; and a word-line insulating film formed on a second surface region adjacent to the first surface region, the second surface region being a part of out of the surface region, the word-line insulating film electrically insulating the semiconductor layer and the word line, wherein the semiconductor layer, the word line and the word-line insulating film form a capacitor, and when a potential difference is given between the word line and the bit line, the word-line insulating film is broken in order to store data.
摘要翻译：本公开涉及包括位线的半导体存储器件; 字线布置成对应于位线和字线的交叉点的半导体层; 连接在第一表面区域和位线之间的位线触点，第一表面区域是指向字线和位线的半导体层的表面区域的一部分; 以及形成在与所述第一表面区域相邻的第二表面区域上的字线绝缘膜，所述第二表面区域是所述表面区域之外的一部分，所述字线绝缘膜使所述半导体层和所述字线电绝缘，其中半导体层，字线和字线绝缘膜形成电容器，并且当在字线和位线之间给出电位差时，字线绝缘膜被破坏以便存储数据。

3. 发明授权

US07692963B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07692963B2
公开(公告)日：2010-04-06
申请号：US11934337
申请日：2007-11-02
申请人： Tomoaki Shino , Akihiro Nitayama , Takeshi Hamamoto , Hideaki Aochi , Takashi Ohsawa , Ryo Fukuda
发明人： Tomoaki Shino , Akihiro Nitayama , Takeshi Hamamoto , Hideaki Aochi , Takashi Ohsawa , Ryo Fukuda
IPC分类号： G11C11/34
CPC分类号： G11C11/404 , G11C11/409 , G11C11/4091 , G11C11/4097 , G11C11/4099 , G11C2211/4016 , H01L21/84 , H01L27/108 , H01L27/10802 , H01L27/10844 , H01L27/1203 , H01L29/7841
摘要： The disclosure concerns a semiconductor memory device comprising a semiconductor layer; a charge trap film in contact with a first surface of the semiconductor layer; a gate insulating film in contact with a second surface of the semiconductor layer, the second surface being opposite to the first surface; a back gate electrode in contact with the charge trap film; a gate electrode in contact with the gate insulating film; a source and a drain formed in the semiconductor layer; and a body region provided between the drain and the source, the body region being in an electrically floating state, wherein a threshold voltage or a drain current of a memory cell including the source, the drain, and the gate electrode is adjusted by changing number of majority carriers accumulated in the body region and a quantity of charges trapped into the charge trap film.
摘要翻译：本公开涉及包括半导体层的半导体存储器件; 与所述半导体层的第一表面接触的电荷陷阱膜; 与所述半导体层的第二表面接触的栅极绝缘膜，所述第二表面与所述第一表面相对; 与电荷陷阱膜接触的背栅电极; 与栅极绝缘膜接触的栅电极; 在半导体层中形成的源极和漏极; 以及设置在所述漏极和源极之间的体区，所述体区域处于电浮置状态，其中通过改变数量来调整包括所述源极，漏极和所述栅电极的存储单元的阈值电压或漏极电流的多数载体积聚在身体区域中，并且一定量的电荷被捕获到电荷陷阱膜中。

4. 发明申请

US20080237695A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20080237695A1
公开(公告)日：2008-10-02
申请号：US11860956
申请日：2007-09-25
申请人： Tomoaki SHINO , Akihiro Nitayama , Takeshi Hamamoto , Hideaki Aochi , Takashi Ohsawa , Ryo Fukuda
发明人： Tomoaki SHINO , Akihiro Nitayama , Takeshi Hamamoto , Hideaki Aochi , Takashi Ohsawa , Ryo Fukuda
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , G11C11/404 , G11C11/4074 , G11C14/0018 , G11C2211/4016 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L27/1203 , H01L29/42344 , H01L29/785 , H01L29/78648
摘要： This disclosure concerns a memory comprising a charge trapping film; a gate insulating film; a back gate on the charge trapping film; a front gate on the gate insulating film; and a body region provided between a drain and a source, wherein the memory includes a first storage state for storing data depending on the number of majority carriers in the body region and a second storage state for storing data depending on the amount of charges in the charge trapping film, and the memory is shifted from the first storage state to the second storage state by converting the number of majority carriers in the body region into the amount of charges in the charge trapping film or from the second storage state to the first storage state by converting the amount of charges in the charge trapping film into the number of majority carriers in the body region.
摘要翻译：本公开涉及包含电荷捕获膜的存储器; 栅极绝缘膜; 电荷捕获膜上的后门; 栅极绝缘膜上的前门; 以及设置在漏极和源极之间的体区，其中所述存储器包括用于根据所述身体区域中的多数载体的数量存储数据的第一存储状态和用于根据所述体内区域中的电荷量存储数据的第二存储状态通过将身体区域中的多数载体的数量转换为电荷俘获膜中的电荷量或从第二存储状态到第一存储器，将存储器从第一存储状态转移到第二存储状态通过将电荷俘获膜中的电荷量转换成体区中的多数载体的数量来进行状态。

5. 发明申请

US20080239789A1 SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：半导体存储器件
公开(公告)号：US20080239789A1
公开(公告)日：2008-10-02
申请号：US11934337
申请日：2007-11-02
申请人： Tomoaki SHINO , Akihiro Nitayama , Takeshi Hamamoto , Hideaki Aochi , Takashi Ohsawa , Ryo Fukuda
发明人： Tomoaki SHINO , Akihiro Nitayama , Takeshi Hamamoto , Hideaki Aochi , Takashi Ohsawa , Ryo Fukuda
IPC分类号： G11C11/24 , H01L27/108 , G11C11/34
CPC分类号： G11C11/404 , G11C11/409 , G11C11/4091 , G11C11/4097 , G11C11/4099 , G11C2211/4016 , H01L21/84 , H01L27/108 , H01L27/10802 , H01L27/10844 , H01L27/1203 , H01L29/7841
摘要： The disclosure concerns a semiconductor memory device comprising a semiconductor layer; a charge trap film in contact with a first surface of the semiconductor layer; a gate insulating film in contact with a second surface of the semiconductor layer, the second surface being opposite to the first surface; a back gate electrode in contact with the charge trap film; a gate electrode in contact with the gate insulating film; a source and a drain formed in the semiconductor layer; and a body region provided between the drain and the source, the body region being in an electrically floating state, wherein a threshold voltage or a drain current of a memory cell including the source, the drain, and the gate electrode is adjusted by changing number of majority carriers accumulated in the body region and a quantity of charges trapped into the charge trap film.
摘要翻译：本公开涉及包括半导体层的半导体存储器件; 与所述半导体层的第一表面接触的电荷陷阱膜; 与所述半导体层的第二表面接触的栅极绝缘膜，所述第二表面与所述第一表面相对; 与电荷陷阱膜接触的背栅电极; 与栅极绝缘膜接触的栅电极; 在半导体层中形成的源极和漏极; 以及设置在所述漏极和源极之间的体区，所述体区域处于电浮置状态，其中通过改变数量来调整包括所述源极，漏极和所述栅电极的存储单元的阈值电压或漏极电流的多数载体积聚在身体区域中，并且一定量的电荷被捕获到电荷陷阱膜中。

6. 发明授权

US07609551B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07609551B2
公开(公告)日：2009-10-27
申请号：US11860956
申请日：2007-09-25
申请人： Tomoaki Shino , Akihiro Nitayama , Takeshi Hamamoto , Hideaki Aochi , Takashi Ohsawa , Ryo Fukuda
发明人： Tomoaki Shino , Akihiro Nitayama , Takeshi Hamamoto , Hideaki Aochi , Takashi Ohsawa , Ryo Fukuda
IPC分类号： G11C14/00 , G11C16/04
CPC分类号： H01L29/792 , G11C11/404 , G11C11/4074 , G11C14/0018 , G11C2211/4016 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L27/1203 , H01L29/42344 , H01L29/785 , H01L29/78648
摘要： This disclosure concerns a memory comprising a charge trapping film; a gate insulating film; a back gate on the charge trapping film; a front gate on the gate insulating film; and a body region provided between a drain and a source, wherein the memory includes a first storage state for storing data depending on the number of majority carriers in the body region and a second storage state for storing data depending on the amount of charges in the charge trapping film, and the memory is shifted from the first storage state to the second storage state by converting the number of majority carriers in the body region into the amount of charges in the charge trapping film or from the second storage state to the first storage state by converting the amount of charges in the charge trapping film into the number of majority carriers in the body region.
摘要翻译：本公开涉及包含电荷捕获膜的存储器; 栅极绝缘膜; 电荷捕获膜上的后门; 栅极绝缘膜上的前门; 以及设置在漏极和源极之间的体区，其中所述存储器包括用于根据所述身体区域中的多数载体的数量存储数据的第一存储状态和用于根据所述体内区域中的电荷量存储数据的第二存储状态通过将身体区域中的多数载体的数量转换为电荷俘获膜中的电荷量或从第二存储状态到第一存储器，将存储器从第一存储状态转移到第二存储状态通过将电荷俘获膜中的电荷量转换成体区中的多数载体的数量来进行状态。

7. 发明申请

US20100019304A1 SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20100019304A1
公开(公告)日：2010-01-28
申请号：US12497010
申请日：2009-07-02
申请人： Yoshihiro MINAMI , Takashi Ohsawa , Tomoaki Shino , Takeshi Hamamoto , Akihiro Nitayama
发明人： Yoshihiro MINAMI , Takashi Ohsawa , Tomoaki Shino , Takeshi Hamamoto , Akihiro Nitayama
IPC分类号： H01L27/06 , H01L21/8249
CPC分类号： H01L27/1022 , G11C2211/4016 , H01L27/108 , H01L27/10802 , H01L29/7841
摘要： A semiconductor memory device includes bodies electrically floating; sources; drains; gate electrodes, each of which is adjacent to one side surface of the one of the bodies via a gate dielectric film; plates, each of which is adjacent to the other side surface of the one of the bodies via a plate dielectric film; first bit lines on the drains, the first bit lines including a semiconductor with a same conductivity type as that of the drains; and emitters on the semiconductor of the first bit lines, the emitters including a semiconductor with an opposite conductivity type to that of the semiconductor of the first bit lines, wherein the emitters are stacked above the bodies and the drains.
摘要翻译：半导体存储器件包括电漂浮体; 来源下水道栅电极，其每一个经由栅极电介质膜与所述一个主体的一个侧表面相邻; 板，其每一个经由板电介质膜与所述一个主体的另一侧表面相邻; 排水口上的第一位线，第一位线包括与排水管相同导电类型的半导体; 和在第一位线的半导体上的发射极，发射器包括与第一位线的半导体的导电类型相反的导电类型的半导体，其中发射体堆叠在主体和漏极之上。

8. 发明授权

US07977738B2 Semiconductor memory device and manufacturing method thereof 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US07977738B2
公开(公告)日：2011-07-12
申请号：US12497010
申请日：2009-07-02
申请人： Yoshihiro Minami , Takashi Ohsawa , Tomoaki Shino , Takeshi Hamamoto , Akihiro Nitayama
发明人： Yoshihiro Minami , Takashi Ohsawa , Tomoaki Shino , Takeshi Hamamoto , Akihiro Nitayama
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L27/1022 , G11C2211/4016 , H01L27/108 , H01L27/10802 , H01L29/7841
摘要： A semiconductor memory device includes bodies electrically floating; sources; drains; gate electrodes, each of which is adjacent to one side surface of the one of the bodies via a gate dielectric film; plates, each of which is adjacent to the other side surface of the one of the bodies via a plate dielectric film; first bit lines on the drains, the first bit lines including a semiconductor with a same conductivity type as that of the drains; and emitters on the semiconductor of the first bit lines, the emitters including a semiconductor with an opposite conductivity type to that of the semiconductor of the first bit lines, wherein the emitters are stacked above the bodies and the drains.
摘要翻译：半导体存储器件包括电漂浮体; 来源下水道栅电极，其每一个经由栅极电介质膜与所述一个主体的一个侧表面相邻; 板，其每一个经由板电介质膜与所述一个主体的另一侧表面相邻; 排水口上的第一位线，第一位线包括具有与排水管相同的导电类型的半导体; 和在第一位线的半导体上的发射极，发射器包括与第一位线的半导体的导电类型相反的导电类型的半导体，其中发射体堆叠在主体和漏极之上。

9. 发明授权

US08643105B2 Semiconductor memory device and manufacturing method thereof 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US08643105B2
公开(公告)日：2014-02-04
申请号：US12263762
申请日：2008-11-03
申请人： Takeshi Hamamoto
发明人： Takeshi Hamamoto
IPC分类号： H01L27/12
CPC分类号： H01L27/108 , H01L21/84 , H01L27/10802 , H01L27/10826 , H01L27/1203 , H01L29/7841 , H01L29/785
摘要： This disclosure concerns a semiconductor memory device including a semiconductor substrate; a buried insulation film provided on the semiconductor substrate; a semiconductor layer provided on the buried insulation film; a source layer and a drain layer provided in the semiconductor layer; a body region provided in the semiconductor layer between the source layer and the drain layer, and being in an electrically floating state, the body region accumulating or discharging charges to store data; a gate dielectric film provided on the body region; a gate electrode provided on the gate dielectric film; and a plate electrode facing a side surface of the body region via an insulation film, in an element isolation region.
摘要翻译：本公开涉及包括半导体衬底的半导体存储器件; 设置在半导体衬底上的掩埋绝缘膜; 设置在所述掩埋绝缘膜上的半导体层; 设置在所述半导体层中的源极层和漏极层; 设置在所述源极层和所述漏极层之间的所述半导体层中并处于电浮动状态的体区，所述体区累积或放电以存储数据; 设置在所述身体区域上的栅极电介质膜; 设置在栅极电介质膜上的栅电极; 以及在元件隔离区域中经由绝缘膜面对主体区域的侧表面的平板电极。

10. 发明授权

US07952162B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07952162B2
公开(公告)日：2011-05-31
申请号：US12541449
申请日：2009-08-14
申请人： Takeshi Hamamoto
发明人： Takeshi Hamamoto
IPC分类号： H01L21/76
CPC分类号： H01L29/7841 , H01L27/108 , H01L27/10802
摘要： A semiconductor device of one embodiment of the present invention includes a substrate; isolation layers, each of which is formed in a trench formed on the substrate and has an insulating film and a conductive layer; a semiconductor layer of a first conductivity type for storing signal charges, formed between the isolation layers and isolated from the conductive layers by the insulating films; a semiconductor layer of a second conductivity type, formed under the semiconductor layer of the first conductivity type; and a transistor having a gate insulator film formed on the semiconductor layer of the first conductivity type and a gate electrode formed on the gate insulator film.
摘要翻译：本发明的一个实施例的半导体器件包括：衬底; 隔离层，其形成在形成在基板上的沟槽中，并且具有绝缘膜和导电层; 用于存储信号电荷的第一导电类型的半导体层，形成在隔离层之间并通过绝缘膜与导电层隔离; 形成在第一导电类型的半导体层下方的第二导电类型的半导体层; 以及具有形成在第一导电类型的半导体层上的栅极绝缘膜和形成在栅极绝缘膜上的栅电极的晶体管。

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