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1. 发明授权

US5432799A Modulating method 失效
标题翻译：调制方式
公开(公告)号：US5432799A
公开(公告)日：1995-07-11
申请号：US64764
申请日：1993-05-19
申请人： Yoshihide Shimpuku , Hiroyuki Ino , Yasuyuki Chaki , Toshiyuki Nakagawa
发明人： Yoshihide Shimpuku , Hiroyuki Ino , Yasuyuki Chaki , Toshiyuki Nakagawa
IPC分类号： G11B7/00 , G11B7/004 , G11B7/0045 , G11B20/14 , H03M7/46 , H03M13/00
CPC分类号： G11B20/1426
摘要： A method of modulating digital data to a variable-length code having parameters d, k, m, n, and r for recording information on and reproducing the same from an optical disc. The optimal range of a minimum run length d corresponding to the minimum number of successive same symbols is determined by a procedure which includes a first step to determine the minimum S/N required for obtaining a desired error rate from the relationship between a bit error rate and the S/N when d=0; a second step to obtain the relationship between a change of the numerical value d and that of the S/N by calculating, on the basis of the required minimum S/N obtained at the first step, the S/N loss caused due to the change of the numerical value d; and a third step to determine, from the relationship between the numerical value d and the S/N, the range of the value d corresponding to the S/N of the transmission characteristic dependent on an optical system and an optical disc.
摘要翻译：将数字数据调制为具有参数d，k，m，n和r的可变长度代码的方法，用于从光盘记录信息并从光盘再现信息。对应于连续相同符号的最小数量的最小游程长度d的最佳范围由包括第一步骤的步骤来确定，该步骤确定从误码率之间的关系中获得期望误码率所需的最小S / N 当d = 0时S / N; 通过基于在第一步骤中获得的所需最小S / N计算由于第一步骤所产生的S / N损失而获得数值d与S / N的变化之间的关系的第二步骤数值变化d; 以及第三步骤，根据数值d和S / N之间的关系，确定与取决于光学系统和光盘的传输特性的S / N相对应的值d的范围。

2. 发明授权

US5355133A Data modulating method and apparatus and data demodulating method and apparatus 失效
标题翻译：数据调制方法及装置及数据解调方法及装置
公开(公告)号：US5355133A
公开(公告)日：1994-10-11
申请号：US15477
申请日：1993-02-09
申请人： Yoshihide Shimpuku , Hiroyuki Ino , Yasuyuki Chaki , Toshiyuki Nakagawa
发明人： Yoshihide Shimpuku , Hiroyuki Ino , Yasuyuki Chaki , Toshiyuki Nakagawa
IPC分类号： G11B20/14 , H03M5/14 , H03M7/40 , H03M5/18
CPC分类号： G11B20/1426 , H03M5/145
摘要： A modulating method and apparatus and a demodulating method and apparatus wherein high density recording can be achieved and a dc component can be controlled with a variable length channel code are disclosed. Recording data are divided into a predetermined plurality of blocks, and those of the recording data at a portion other than a boundary portion of each of the blocks are coded referring to a table of a first ROM so that data of m bits may be converted into a code of n bits. The remaining data at the boundary portion of each block are converted into a code referring to another table of second ROM so that data of m bits may be converted into a code of n bits. Further, a code of n bits for minimizing a dc component is produced referring to a third table of a further ROM and is added to the code generated by the first and second ROMs.
摘要翻译：公开了可以实现高密度记录并且可以用可变长度信道码来控制直流分量的调制方法和装置以及解调方法和装置。记录数据被划分为预定的多个块，并且在每个块的边界部分之外的部分处的记录数据的那些被编码，参考第一ROM的表，使得m位的数据可以被转换成 n位的代码。每个块的边界部分的剩余数据被转换成参考第二ROM的另一个表的代码，使得m位的数据可以被转换成n位的代码。此外，参考另一ROM的第三表产生用于最小化直流分量的n位的代码，并将其添加到由第一和第二ROM产生的代码中。

3. 发明授权

US5537422A Synchronization signal detector, synchronization signal detecting method and demodulator 失效
标题翻译：同步信号检测器，同步信号检测方法和解调器
公开(公告)号：US5537422A
公开(公告)日：1996-07-16
申请号：US565620
申请日：1995-11-22
申请人： Yoshihide Shimpuku , Hiroyuki Ino , Yasuyuki Chaki , Toshiyuki Nakagawa
发明人： Yoshihide Shimpuku , Hiroyuki Ino , Yasuyuki Chaki , Toshiyuki Nakagawa
IPC分类号： G11B20/12 , G11B20/14 , G11B27/30 , H03M5/06 , H03M7/14 , H03M7/40 , H03M13/00
CPC分类号： G11B20/1403 , G11B20/1426 , G11B27/3027 , G11B20/1217 , G11B2220/2545
摘要： A synchronization detector includes a NRZI circuit for extracting edge portions of RF signals detected as binary-valued signals to form a pulse train, a counter for counting the number of channel clocks in the distance between transitions represented by the edge portions, a latch circuit operated responsive to pulses from the NRZI circuit for holding a number of previously counted channel clocks immediately preceding a current count of channel clocks, and AND gates and an OR gate for detecting synchronization signals when the combination of the channel clocks from the counter and the latch circuit is the combination of the maximum distance between transitions Tmax and Tmax-kT (k=1 or 2) of a (d, k; m, n; r) modulation code. Synchronization signals may be detected promptly even if the frame structure is increased in size to enable restoration of synchronization to be expedited when frame structure synchronization is not in order. A demodulator utilizing the synchronization signal detector is also disclosed.
摘要翻译：同步检测器包括：NRZI电路，用于提取被检测为二进制值信号的RF信号的边缘部分以形成脉冲序列;计数器，用于计数由边缘部分表示的跃迁之间的距离的信道时钟数;锁存电路，响应于来自NRZI电路的脉冲，用于保持紧邻当前通道时钟计数之前的多个先前计数的通道时钟;以及与门和用于检测同步信号的或门，当来自计数器和锁存电路的通道时钟的组合是（d，k; m，n; r）调制码的转换Tmax和Tmax-kT（k = 1或2）之间的最大距离的组合。即使框架结构的大小增加，也可以及时检测同步信号，以便在帧结构同步不顺序时能够恢复同步。还公开了利用同步信号检测器的解调器。

4. 发明授权

US5469162A Data modulation method 失效
标题翻译：数据调制方式
公开(公告)号：US5469162A
公开(公告)日：1995-11-21
申请号：US039730
申请日：1993-03-30
申请人： Yasuyuki Chaki , Yoshihide Shimpuku , Hiroyuki Ino
发明人： Yasuyuki Chaki , Yoshihide Shimpuku , Hiroyuki Ino
IPC分类号： G11B20/14 , H03M5/14 , H03M7/14 , H03M7/00
CPC分类号： H03M5/145 , G11B20/1426
摘要： In a data modulation method, m-bit data is modulated to n-bit data (n.gtoreq.m) having fewer direct current and low frequency components. A dispersion of the digital sum variation of code weights can be reduced, a direct current component is reduced and an error rate can be further reduced by selecting a plurality of modulation tables constituting the combination of one or more sub-groups of modulation data obtained by dividing a group of modulation data by a code weight having the same value based on the digital sum variation of the code weights accumulated until a time at which m-bit data is converted to n-bit code and converting next m-bit data continuously to present m-bit data to n-bit code by using the modulation tables.
摘要翻译：在数据调制方法中，m位数据被调制成具有较少直流和低频分量的n位数据（n> / = m）。可以减少代码权重的数字和变化的偏差，通过选择构成由一个或多个调制数据的子组合组成的多个调制表来减少直流分量并且可以进一步降低错误率，将一组调制数据除以具有相同值的代码权重，该代码权重基于累积的代码权重的数字和变化，直到将m位数据转换为n位代码并将下一个m位数据连续转换为通过使用调制表将m位数据提供给n位代码。

5. 发明授权

US5357524A Apparatus for converting a digital signal 失效
标题翻译：用于转换数字信号的装置
公开(公告)号：US5357524A
公开(公告)日：1994-10-18
申请号：US21237
申请日：1993-02-23
申请人： Yoshihide Shimpuku , Hiroyuki Ino , Yasuyuki Chaki
发明人： Yoshihide Shimpuku , Hiroyuki Ino , Yasuyuki Chaki
IPC分类号： G11B20/10 , G11B20/14 , G11B20/18 , H03M13/23 , G06F11/00
CPC分类号： G11B20/10055 , G11B20/10009 , G11B20/10296 , G11B20/1426 , G11B20/1813
摘要： A maximum likelihood decoder (28) comprises a Viterbi decoding unit (30) and a symbol concluding unit (29). Final N-M bit data of data of N (>M) bit unit, to which M-bit original data is converted, is supplied to the symbol concluding unit (29) as a terminal portion and other data is supplied to the Viterbi decoding unit (30), thereby being demodulated by a demodulator (37). A maximum likelihood decoding apparatus is provided in which image data or the like can be recorded and reproduced at high speed and maximum likelihood parallel decoding is effected. A reproducing data demodulating apparatus using such maximum likelihood decoding apparatus is also provided.
摘要翻译：最大似然解码器（28）包括维特比解码单元（30）和符号结束单元（29）。将M位原始数据转换到的N（> M）位单元的数据的最终NM位数据提供给作为终端部分的符号结束单元（29），并且其他数据被提供给维特比解码单元 30），由解调器（37）进行解调。提供了一种最大似然解码装置，其中可以高速度地记录和再现图像数据等，并且进行最大似然并行解码。还提供了使用这种最大似然解码装置的再现数据解调装置。

6. 发明授权

US5138314A Method for converting and/or detecting data 失效
标题翻译：转换和/或检测数据的方法
公开(公告)号：US5138314A
公开(公告)日：1992-08-11
申请号：US728732
申请日：1991-07-11
申请人： Yoshihide Shimpuku , Hiroyuki Ino , Yasuyuki Chaki
发明人： Yoshihide Shimpuku , Hiroyuki Ino , Yasuyuki Chaki
IPC分类号： G11B20/10 , G11B20/14
CPC分类号： G11B20/10101 , G11B20/10009 , G11B20/1426
摘要： In a data conversion method of converting source data of M bit unit to be recorded on a recording medium into conversion data of N (>M) bit unit, n, which is a number of inter-symbol interferences permitted in a transmission path, continuous codes in the codes of the conversion data are weighted with a weighting distribution decreasing linearly from a distribution center, the weighted n continuous codes are sequentially added to form the intermediate series, and then such conversion data that the sum of absolute values of differences of codes between the intermediate series (i.e., the code length) is more than a predetermined number of times as large as a reference value of the weighting coefficient is selected as a modulation code, whereby the pattern length between the code patterns can be made larger to thereby improve the recording density remarkably with using the present recording medium and recording and/or reproducing apparatus. Further, the pattern of the reproduced signal corresponding to the data to be detected is compared with a code pattern group corresponding to each conversion data to select a similar pattern so that the conversion data recorded at a remarkably high recording density can be positively detected while using the present recording medium and recording and/or reproducing apparatus.

7. 发明授权

US5400023A Modulating method and demodulating method as well as modulating apparatus and demodulating apparatus 失效
标题翻译：调制方法和解调方法以及调制装置和解调装置
公开(公告)号：US5400023A
公开(公告)日：1995-03-21
申请号：US29133
申请日：1993-03-10
申请人： Hiroyuki Ino , Yoshihide Shimpuku , Yasuyuki Chaki , Toshiyuki Nakagawa
发明人： Hiroyuki Ino , Yoshihide Shimpuku , Yasuyuki Chaki , Toshiyuki Nakagawa
IPC分类号： G11B20/14 , H03M5/14 , H03M7/46
CPC分类号： H03M5/145 , G11B20/1426
摘要： A modulating method and apparatus and a demodulating method and apparatus in which a variable length code (d, k;m, n;r) which can provide a greater minimum reversal distance to allow recording of a higher density than ever is provided. According to the modulating method and apparatus, digital data of a basic data length of m bits is modulated into a variable length code (d, k;m, n;r) of a basic code length of n bits, and where the distance between adjacent ones of the digital data is represented by T, the minimum reversal distance of the variable length code is equal to or greater than 2.0 T and the minimum length of a run of a same symbol is equal to or greater than 4. The demodulating apparatus demodulates the digital data back into the variable length code and comprises storage means for storing therein a plurality of tables for converting the digital data into the variable length code, discriminating means for discriminating the binding length of the digital data, and selecting means for selecting one of the tables in accordance with a result of discrimination of the discriminating means.
摘要翻译：提供了可以提供更大的最小反转距离以允许记录比以往更高密度的可变长度码（d，k; m，n; r）的调制方法和装置以及解调方法和装置。根据调制方法和装置，m比特的基本数据长度的数字数据被调制成n比特的基本码长度的可变长度码（d，k; m，n; r），并且其中数字数据中的相邻数字由T表示，可变长度码的最小反转距离等于或大于2.0T，同一符号的行程的最小长度等于或大于4.解调装置将数字数据解调回可变长度码，并且包括用于在其中存储用于将数字数据转换成可变长度码的多个表的存储装置，用于鉴别数字数据的绑定长度的鉴别装置，以及用于选择一个根据识别装置的辨别结果。

8. 发明授权

US6014096A Data decoding method and device 失效
标题翻译：数据解码方法及装置
公开(公告)号：US6014096A
公开(公告)日：2000-01-11
申请号：US947429
申请日：1997-10-08
申请人： Toshiyuki Nakagawa , Hiroyuki Ino , Shunji Yoshimura , Shinichi Kai , Yoshihide Shimpuku , Michihiko Iida , Tetsuji Kawashima , Shoji Sato
发明人： Toshiyuki Nakagawa , Hiroyuki Ino , Shunji Yoshimura , Shinichi Kai , Yoshihide Shimpuku , Michihiko Iida , Tetsuji Kawashima , Shoji Sato
IPC分类号： G11B20/10 , G11B20/14 , H03M7/00 , H03M7/14 , H04L25/49 , H03M5/06 , G11B5/09 , H03M7/46
CPC分类号： G11B20/1426 , G11B20/10009
摘要： If there is any portion in channel bit data obtained on converting a signal read out from a recording medium into a bi-level signal which fails to satisfy a condition concerning a minimum run length or a maximum run length of the same symbol, the channel bit data is corrected to improve the bit error rate to secure a skew margin. To this end, channel bit data not satisfying a minimum run length d' of the same symbol is detected by a (d'-1) detector 4 using n-tupled clocks obtained on n-tupling channel clocks of playback data by a bit clock generator 2, where n is an integer not less than 2. A correction position of the channel bit data having the run length of the same symbol equal to (d'-1) is designated by a correction bit position designating unit 5. A data correction unit 6 then corrects the channel bit data so that the minimum run length of the same symbol will be equal to d'.
摘要翻译：如果在将从记录介质读出的信号转换成不能满足与相同符号的最小游程长度或最大游程长度有关的条件的双电平信号中获得的通道位数据中存在任何部分，则通道位校正数据以提高误码率以确保偏斜裕度。为此，由（d'-1）检测器4检测不满足相同符号的最小游程长度d'的通道位数据，使用通过位时钟在重放数据的n个tupling通道时钟上获得的n个元组时钟发生器2，其中n是不小于2的整数。具有相同符号的游程长度等于（d'-1）的通道位数据的校正位置由校正位位置指定单元5指定。数据校正单元6然后校正通道位数据，使得相同符号的最小游程长度将等于d'。

9. 发明授权

US5646966A Method and apparatus for detecting synchronizing signals by latching successived count values that represent time between received sync pulses for comparison to a predetermined sync pattern of count values 失效
标题翻译：用于通过锁存表示接收到的同步脉冲之间的时间的连续计数值来检测同步信号的方法和装置，用于与计数值的预定同步模式进行比较
公开(公告)号：US5646966A
公开(公告)日：1997-07-08
申请号：US84860
申请日：1993-06-29
申请人： Yasuyuki Chaki , Hiroyuki Ino
发明人： Yasuyuki Chaki , Hiroyuki Ino
IPC分类号： G11B20/10 , G11B20/14 , G11B20/22 , G11B27/30 , H04L7/00
CPC分类号： G11B27/3027 , G11B20/14 , G11B20/225
摘要： A synchronization signal detector for detecting synchronization signals or frame synchronization signals recorded on a recording medium includes a binary-valued signal detector for translating RF signals into binary-valued signals, an edge detection circuit for extracting edge portions of the binary-valued signals, a counter for counting the number of clocks generated by an external source between the edge portions, a number of latch circuits for holding successive clock count values between the edge portions and for successively shifting the clock values held by them, value coincidence circuits for comparing the numbers of clocks between transitions of the synchronization patterns and the clock count values held by the counter and the latch circuits and for outputting a signal indicating a coincidence in case of complete coincidence between the numbers of clocks and the clock count values and an AND circuit for taking a logical sum of the outputs of the value coincidence circuits and the edge detector for producing a detection output of the synchronization signal. The synchronization signal may be detected efficiently with a short delay time and by a simple circuit construction even if the synchronization signal pattern is of a longer length. A demodulator utilizing the synchronization signal detector is also disclosed.
摘要翻译：用于检测记录在记录介质上的同步信号或帧同步信号的同步信号检测器包括用于将RF信号转换成二值信号的二进制值信号检测器，用于提取二进制值信号的边缘部分的边缘检测电路，用于对边缘部分之间的外部源产生的时钟数进行计数的计数器，用于在边缘部分之间保持连续时钟计数值并且用于连续移位它们保持的时钟值的多个锁存电路，用于比较数字的值一致电路在同步模式的转换之间的时钟和由计数器和锁存电路保持的时钟计数值之间的时钟，并且用于在时钟数和时钟计数值之间完全一致的情况下输出指示一致的信号，以及用于采取的AND电路值符合电路的输出的逻辑和边缘检测器，用于产生同步信号的检测输出。即使同步信号图案具有较长的长度，也可以以短的延迟时间和简单的电路结构有效地检测同步信号。还公开了利用同步信号检测器的解调器。

10. 发明授权

US09829208B2 Operating terminal for air conditioner 有权
公开(公告)号：US09829208B2
公开(公告)日：2017-11-28
申请号：US14384742
申请日：2013-01-09
申请人： Hiroyuki Ino , Hidetoshi Muramatsu
发明人： Hiroyuki Ino , Hidetoshi Muramatsu
IPC分类号： G05B21/00 , F24F11/00 , G08C17/02 , G05D23/19
CPC分类号： F24F11/0009 , F24F11/30 , F24F11/56 , G05D23/1917 , G08C17/02
摘要： An operating terminal that is capable of controlling an air conditioner including an indoor device and an outdoor device. The operating terminal includes a display unit that displays at least state information of an air conditioner, a memory that stores therein setting information recorded on an outdoor/indoor control substrate, a communication unit that performs information communication with the indoor device, and an information processing unit that reads setting information set in the outdoor/indoor control substrate through the communication unit, records this setting information 32a in the memory, and causes the display unit to display the setting information.

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