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1. 发明授权

US08671773B2 Electronic flow meter 有权
标题翻译：电子流量计
公开(公告)号：US08671773B2
公开(公告)日：2014-03-18
申请号：US13482873
申请日：2012-05-29
申请人： Yoshiharu Ono , Osamu Karino , Yoshihiro Shimizu , Yoshihiro Miyagawa , Hiroyuki Kawajiri , Takehiro Furukawa
发明人： Yoshiharu Ono , Osamu Karino , Yoshihiro Shimizu , Yoshihiro Miyagawa , Hiroyuki Kawajiri , Takehiro Furukawa
IPC分类号： G01F1/56
CPC分类号： G01F1/075 , G01F15/068
摘要： An electronic flow meter includes a magnetic sensor, phase-A and phase-B drivers, a phase-A comparator, a phase-B comparator, a two-phase encoder, and a rotational speed timer. The two-phase encoder determines a normal/reverse direction where the impeller is rotated based on event signals sampled by the phase-A and the phase-B comparators, respectively, causing a counter to count up or to count down according to the normal/reverse direction as determined, thereby outputting an event count signal. The rotational speed timer calculates a rotational frequency of the impeller from the event count signal outputted by the two-phase encoder and sets frequencies of respective sampling signals of the phase-A and the phase-B comparators at a time when the rotational frequency of the impeller is measured next, and respective drive periods of the phase-A and the phase-B drivers in accordance with the rotational frequency of the impeller as calculated.
摘要翻译：电子流量计包括磁传感器，A相和B相驱动器，A相比较器，B相比较器，两相编码器和转速计时器。两相编码器基于由相位A和相位B比较器采样的事件信号分别确定叶轮旋转的正/反方向，使得计数器根据正常/反相计数器向上计数或倒计数，由此输出事件计数信号。旋转速度计时器根据由两相编码器输出的事件计数信号计算叶轮的旋转频率，并设定相位A和相位-B比较器的各个采样信号的频率，叶轮，根据计算出的叶轮的转速，相位-A和相位B驱动器的驱动周期相应地被测量。

2. 发明授权

US08219731B2 Data processor and control system 失效
标题翻译：数据处理器和控制系统
公开(公告)号：US08219731B2
公开(公告)日：2012-07-10
申请号：US13287016
申请日：2011-11-01
申请人： Hidemi Oyama , Masanobu Kawamura , Takuya Ikeguchi , Masanori Matsumoto , Hiroyuki Kawajiri
发明人： Hidemi Oyama , Masanobu Kawamura , Takuya Ikeguchi , Masanori Matsumoto , Hiroyuki Kawajiri
IPC分类号： G06F13/24 , G06F3/00
CPC分类号： G06F13/24 , G06F9/3861 , G06F9/3865
摘要： Provided are a data processor, and a control system, in which an interrupt controller and an event link controller are adopted. The event link controller responds to a generated event signal to output a start control signal for controlling start of an operation of a circuit module. The circuit module is able to generate an event signal. The event link controller generates the start control signal according to the correspondences between event signals and start control signals which are defined by event control information. The links between the event signals and start control signals can be prescribed by the event control information. Therefore, operations of circuit modules prescribed by such links can be controlled sequentially. The control neither involves save and return processes by CPU as in the interrupt processing, nor needs priority level control as executed on competing interrupt requests.
摘要翻译：提供了一种数据处理器和控制系统，其中采用了中断控制器和事件链路控制器。事件链接控制器响应生成的事件信号以输出用于控制电路模块的操作开始的起始控制信号。电路模块能够产生事件信号。事件链路控制器根据由事件控制信息定义的事件信号和起始控制信号之间的对应关系生成启动控制信号。事件信号和启动控制信号之间的链接可以由事件控制信息来规定。因此，可以顺序地控制由这种链路规定的电路模块的操作。该控制既不包括中断处理中的CPU保存和返回进程，也不需要在竞争中断请求中执行优先级控制。

3. 发明申请

US20120260014A1 DATA PROCESSOR AND CONTROL SYSTEM 有权
标题翻译：数据处理器和控制系统
公开(公告)号：US20120260014A1
公开(公告)日：2012-10-11
申请号：US13527312
申请日：2012-06-19
申请人： Hidemi OYAMA , Masanobu Kawamura , Takuya Ikeguchi , Masanori Matsumoto , Hiroyuki Kawajiri
发明人： Hidemi OYAMA , Masanobu Kawamura , Takuya Ikeguchi , Masanori Matsumoto , Hiroyuki Kawajiri
IPC分类号： G06F13/24
CPC分类号： G06F13/24 , G06F9/3861 , G06F9/3865
摘要： Provided are a data processor, and a control system, in which an interrupt controller and an event link controller are adopted. The event link controller responds to a generated event signal to output a start control signal for controlling start of an operation of a circuit module. The circuit module is able to generate an event signal. The event link controller generates the start control signal according to the correspondences between event signals and start control signals which are defined by event control information. The links between the event signals and start control signals can be prescribed by the event control information. Therefore, operations of circuit modules prescribed by such links can be controlled sequentially. The control neither involves save and return processes by CPU as in the interrupt processing, nor needs priority level control as executed on competing interrupt requests.
摘要翻译：提供了一种数据处理器和控制系统，其中采用了中断控制器和事件链路控制器。事件链接控制器响应生成的事件信号以输出用于控制电路模块的操作开始的起始控制信号。电路模块能够产生事件信号。事件链路控制器根据由事件控制信息定义的事件信号和起始控制信号之间的对应关系生成启动控制信号。事件信号和启动控制信号之间的链接可以由事件控制信息来规定。因此，可以顺序地控制由这种链路规定的电路模块的操作。该控制既不包括中断处理中的CPU保存和返回进程，也不需要在竞争中断请求中执行优先级控制。

4. 发明申请

US20120047301A1 DATA PROCESSOR AND CONTROL SYSTEM 失效
公开(公告)号：US20120047301A1
公开(公告)日：2012-02-23
申请号：US13287016
申请日：2011-11-01
申请人： Hidemi OYAMA , Masanobu Kawamura , Takuya Ikeguchi , Masanori Matsumoto , Hiroyuki Kawajiri
发明人： Hidemi OYAMA , Masanobu Kawamura , Takuya Ikeguchi , Masanori Matsumoto , Hiroyuki Kawajiri
IPC分类号： G06F13/24
CPC分类号： G06F13/24 , G06F9/3861 , G06F9/3865
摘要： Provided are a data processor, and a control system, in which an interrupt controller and an event link controller are adopted. The event link controller responds to a generated event signal to output a start control signal for controlling start of an operation of a circuit module. The circuit module is able to generate an event signal. The event link controller generates the start control signal according to the correspondences between event signals and start control signals which are defined by event control information. The links between the event signals and start control signals can be prescribed by the event control information. Therefore, operations of circuit modules prescribed by such links can be controlled sequentially. The control neither involves save and return processes by CPU as in the interrupt processing, nor needs priority level control as executed on competing interrupt requests.

5. 发明申请

US20080221708A1 DATA PROCESSOR AND CONTROL SYSTEM 有权
标题翻译：数据处理器和控制系统
公开(公告)号：US20080221708A1
公开(公告)日：2008-09-11
申请号：US12044667
申请日：2008-03-07
申请人： Hidemi Oyama , Masanobu Kawamura , Takuya Ikeguchi , Masanori Matsumoto , Hiroyuki Kawajiri
发明人： Hidemi Oyama , Masanobu Kawamura , Takuya Ikeguchi , Masanori Matsumoto , Hiroyuki Kawajiri
IPC分类号： G06F17/00
CPC分类号： G06F13/24 , G06F9/3861 , G06F9/3865
摘要： Provided are a data processor, and a control system, in which an interrupt controller and an event link controller are adopted. The event link controller responds to a generated event signal to output a start control signal for controlling start of an operation of a circuit module. The circuit module is able to generate an event signal. The event link controller generates the start control signal according to the correspondences between event signals and start control signals which are defined by event control information. The links between the event signals and start control signals can be prescribed by the event control information. Therefore, operations of circuit modules prescribed by such links can be controlled sequentially. The control neither involves save and return processes by CPU as in the interrupt processing, nor needs priority level control as executed on competing interrupt requests.
摘要翻译：提供了一种数据处理器和控制系统，其中采用了中断控制器和事件链路控制器。事件链接控制器响应生成的事件信号以输出用于控制电路模块的操作开始的起始控制信号。电路模块能够产生事件信号。事件链路控制器根据由事件控制信息定义的事件信号和起始控制信号之间的对应关系生成启动控制信号。事件信号和启动控制信号之间的链接可以由事件控制信息来规定。因此，可以顺序地控制由这种链路规定的电路模块的操作。该控制既不包括中断处理中的CPU保存和返回进程，也不需要在竞争中断请求中执行优先级控制。

6. 发明授权

US08489788B2 Data processor and control system 有权
公开(公告)号：US08489788B2
公开(公告)日：2013-07-16
申请号：US13527312
申请日：2012-06-19
申请人： Hidemi Oyama , Masanobu Kawamura , Takuya Ikeguchi , Masanori Matsumoto , Hiroyuki Kawajiri
发明人： Hidemi Oyama , Masanobu Kawamura , Takuya Ikeguchi , Masanori Matsumoto , Hiroyuki Kawajiri
IPC分类号： G06F13/24 , G06F3/00
CPC分类号： G06F13/24 , G06F9/3861 , G06F9/3865
摘要： Provided are a data processor, and a control system, in which an interrupt controller and an event link controller are adopted. The event link controller responds to a generated event signal to output a start control signal for controlling start of an operation of a circuit module. The circuit module is able to generate an event signal. The event link controller generates the start control signal according to the correspondences between event signals and start control signals which are defined by event control information. The links between the event signals and start control signals can be prescribed by the event control information. Therefore, operations of circuit modules prescribed by such links can be controlled sequentially. The control neither involves save and return processes by CPU as in the interrupt processing, nor needs priority level control as executed on competing interrupt requests.

7. 发明授权

US08074005B2 Data processor and control system 有权
标题翻译：数据处理器和控制系统
公开(公告)号：US08074005B2
公开(公告)日：2011-12-06
申请号：US12886766
申请日：2010-09-21
申请人： Hidemi Oyama , Masanobu Kawamura , Takuya Ikeguchi , Masanori Matsumoto , Hiroyuki Kawajiri
发明人： Hidemi Oyama , Masanobu Kawamura , Takuya Ikeguchi , Masanori Matsumoto , Hiroyuki Kawajiri
IPC分类号： G06F13/24 , G06F3/00
CPC分类号： G06F13/24 , G06F9/3861 , G06F9/3865
摘要： Provided are a data processor, and a control system, in which an interrupt controller and an event link controller are adopted. The event link controller responds to a generated event signal to output a start control signal for controlling start of an operation of a circuit module. The circuit module is able to generate an event signal. The event link controller generates the start control signal according to the correspondences between event signals and start control signals which are defined by event control information. The links between the event signals and start control signals can be prescribed by the event control information. Therefore, operations of circuit modules prescribed by such links can be controlled sequentially. The control neither involves save and return processes by CPU as in the interrupt processing, nor needs priority level control as executed on competing interrupt requests.
摘要翻译：提供了一种数据处理器和控制系统，其中采用了中断控制器和事件链路控制器。事件链接控制器响应生成的事件信号以输出用于控制电路模块的操作开始的起始控制信号。电路模块能够产生事件信号。事件链路控制器根据由事件控制信息定义的事件信号和起始控制信号之间的对应关系生成启动控制信号。事件信号和启动控制信号之间的链接可以由事件控制信息来规定。因此，可以顺序地控制由这种链路规定的电路模块的操作。该控制既不包括中断处理中的CPU保存和返回进程，也不需要在竞争中断请求中执行优先级控制。

8. 发明授权

US07822899B2 Data processor and control system 有权
标题翻译：数据处理器和控制系统
公开(公告)号：US07822899B2
公开(公告)日：2010-10-26
申请号：US12044667
申请日：2008-03-07
申请人： Hidemi Oyama , Masanobu Kawamura , Takuya Ikeguchi , Masanori Matsumoto , Hiroyuki Kawajiri
发明人： Hidemi Oyama , Masanobu Kawamura , Takuya Ikeguchi , Masanori Matsumoto , Hiroyuki Kawajiri
IPC分类号： G06F13/24 , G06F3/00
CPC分类号： G06F13/24 , G06F9/3861 , G06F9/3865
摘要： Provided are a data processor, and a control system, in which an interrupt controller and an event link controller are adopted. The event link controller responds to a generated event signal to output a start control signal for controlling start of an operation of a circuit module. The circuit module is able to generate an event signal. The event link controller generates the start control signal according to the correspondences between event signals and start control signals which are defined by event control information. The links between the event signals and start control signals can be prescribed by the event control information. Therefore, operations of circuit modules prescribed by such links can be controlled sequentially. The control neither involves save and return processes by CPU as in the interrupt processing, nor needs priority level control as executed on competing interrupt requests.
摘要翻译：提供了一种数据处理器和控制系统，其中采用了中断控制器和事件链路控制器。事件链接控制器响应生成的事件信号以输出用于控制电路模块的操作开始的起始控制信号。电路模块能够产生事件信号。事件链路控制器根据由事件控制信息定义的事件信号和起始控制信号之间的对应关系生成启动控制信号。事件信号和启动控制信号之间的链接可以由事件控制信息来规定。因此，可以顺序地控制由这种链路规定的电路模块的操作。该控制既不包括中断处理中的CPU保存和返回进程，也不需要在竞争中断请求中执行优先级控制。

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