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    • 3. 发明授权
    • Semiconductor memory capable of debugging an incorrect write to or an incorrect erase from the same
    • 半导体存储器能够调试不正确的写入或不正确的擦除
    • US06535442B2
    • 2003-03-18
    • US10015597
    • 2001-12-17
    • Shinsuke Kumakura
    • Shinsuke Kumakura
    • G11C2900
    • G11C29/00
    • A command storing control circuit stores in storing units a plurality of commands supplied the latest of the supplied commands so as to execute the memory operation. A command reading control circuit reads the commands stored in a command storing area during a test mode. If incorrect data are written into a semiconductor memory, causing the system mounting the semiconductor memory to become inoperable, the cause of the trouble can be efficiently determined by utilizing the commands stored in the command storing area. As a result, the efficiency of development of the system can be improved, for example, and the cost of developing the system can be reduced. Moreover, the quality of the system can be also improved.
    • 命令存储控制电路在存储单元中存储提供最近提供的命令的多个命令,以便执行存储器操作。 命令读取控制电路在测试模式期间读取存储在命令存储区域中的命令。 如果不正确的数据被写入到半导体存储器中,导致半导体存储器的系统安装变得不可操作,则可以通过利用存储在命令存储区域中的命令来有效地确定故障的原因。 结果,可以提高系统的开发效率,例如,可以降低开发系统的成本。 此外,系统的质量也可以提高。
    • 4. 发明授权
    • Semiconductor memory and test method incorporating selectable clock
signal modes
    • 半导体存储器和包含可选时钟信号模式的测试方法
    • US5892776A
    • 1999-04-06
    • US583938
    • 1996-01-11
    • Shinsuke Kumakura
    • Shinsuke Kumakura
    • G01R31/28G11C16/02G11C16/06G11C17/00G11C29/00G11C29/06G11C29/14G11C29/56
    • G11C29/14
    • A semiconductor memory is provided with a select circuit and a control circuit. The select circuit selects either a master clock signal or a test clock signal supplied to a specific terminal, based upon a mode selection signal supplied to a specific terminal. The control operation writes, reads and erases data of the memory cells in response to the master clock signal or the test clock signal. A semiconductor memory test method includes a number of steps, including supplying a mode selection signal, which is higher than normally used voltage, to a specific terminal, and a test clock signal is supplied to another specific terminal; the master clock signal and the test clock signal are then switched in response to the mode selection signal; the data writes and erases relating to the cells of the memory are then tested based upon the test clock signal. In other semiconductor memory test method, two or more specific terminals are first selected, and are supplied with a mode selection signal which is higher than a normally used voltage; then, a master clock signal with a predetermined frequency is selected based upon the mode selection signal. The data writes and erases relating to the cells of the memory are tested based upon the master clock signal with the predetermined frequency.
    • 半导体存储器设置有选择电路和控制电路。 选择电路基于提供给特定终端的模式选择信号来选择提供给特定终端的主时钟信号或测试时钟信号。 控制操作响应于主时钟信号或测试时钟信号写入,读取和擦除存储器单元的数据。 半导体存储器测试方法包括多个步骤,包括将比常用电压高的模式选择信号提供给特定终端,并且将测试时钟信号提供给另一个特定终端; 然后响应于模式选择信号切换主时钟信号和测试时钟信号; 然后基于测试时钟信号测试与存储器的单元相关的数据写入和擦除。 在其他半导体存储器测试方法中,首先选择两个或多个特定端子,并且提供比正常使用的电压高的模式选择信号; 然后,基于模式选择信号选择具有预定频率的主时钟信号。 基于具有预定频率的主时钟信号测试与存储器的单元相关的数据写入和擦除。