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1. 发明授权

US06278155B1 P-channel MOSFET semiconductor device having a low on resistance 有权
标题翻译：具有低导通电阻的P沟道MOSFET半导体器件
公开(公告)号：US06278155B1
公开(公告)日：2001-08-21
申请号：US09444299
申请日：1999-11-22
申请人： Yoshifumi Okabe , Mitsuhiro Kataoka , Yutaka Tomatsu
发明人： Yoshifumi Okabe , Mitsuhiro Kataoka , Yutaka Tomatsu
IPC分类号： H01L29792
CPC分类号： H01L29/7813 , H01L29/0847 , H01L29/086 , H01L29/66348 , H01L29/7397
摘要： In a semiconductor device having a substrate, a p-type semiconductor layer, an n-type channel well region, a p-type lightly doped source region, and a source electrode formed on the substrate in this order, a p-type heavily-doped-source region, an impurity concentration of which is higher than that of the lightly-doped source region, is formed in a surface region of the lightly-doped source region. The source electrode is formed to contact the heavily-doped source region. As a result, a punch through phenomenon between the p-type source region and the p-type semiconductor layer through the n-type channel well region can be prevented without increasing in the On resistance of the semiconductor device.
摘要翻译：在具有衬底，p型半导体层，n型沟道阱区，p型轻掺杂源极区域和在该衬底上形成的源极电极的半导体器件中，在轻掺杂源极区域的表面区域中形成杂质浓度高于轻掺杂源极区域的掺杂源极区域。源电极形成为接触重掺杂源极区。结果，可以在不增加半导体器件的导通电阻的情况下，防止通过n型沟道阱区域的p型源极区域和p型半导体层之间的穿透现象。

2. 发明授权

US6114207A Method of producing a semiconductor device 有权
标题翻译：半导体装置的制造方法
公开(公告)号：US6114207A
公开(公告)日：2000-09-05
申请号：US244605
申请日：1999-02-10
申请人： Yoshifumi Okabe , Mitsuhiro Kataoka , Yutaka Tomatsu
发明人： Yoshifumi Okabe , Mitsuhiro Kataoka , Yutaka Tomatsu
IPC分类号： H01L21/331 , H01L21/336 , H01L29/08 , H01L29/739 , H01L29/78 , H01L29/792
CPC分类号： H01L29/7813 , H01L29/66348 , H01L29/7397 , H01L29/0847
摘要： In a semiconductor device having a substrate, a p-type semiconductor layer, an n-type channel well region, a p-type lightly doped source region, and a source electrode formed on the substrate in this order, a p-type heavily-doped source region, an impurity concentration of which is higher than that of the lightly-doped source region, is formed in a surface region of the lightly-doped source region. The source electrode is formed to contact the heavily-doped source region. As a result, a punch through phenomenon between the p-type source region and the p-type semiconductor layer through the n-type channel well region can be prevented without increasing in the On resistance of the semiconductor device.
摘要翻译：在具有衬底，p型半导体层，n型沟道阱区，p型轻掺杂源极区域和在该衬底上形成的源极电极的半导体器件中，在轻掺杂源极区域的表面区域中形成杂质浓度高于轻掺杂源极区域的掺杂源极区域。源电极形成为接触重掺杂源极区。结果，可以在不增加半导体器件的导通电阻的情况下，防止通过n型沟道阱区域的p型源极区域和p型半导体层之间的穿透现象。

3. 发明授权

US5877527A Semiconductor device and method of producing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US5877527A
公开(公告)日：1999-03-02
申请号：US847599
申请日：1997-04-25
申请人： Yoshifumi Okabe , Mitsuhiro Kataoka , Yutaka Tomatsu
发明人： Yoshifumi Okabe , Mitsuhiro Kataoka , Yutaka Tomatsu
IPC分类号： H01L21/331 , H01L21/336 , H01L29/08 , H01L29/739 , H01L29/78 , H01L29/792
CPC分类号： H01L29/7813 , H01L29/66348 , H01L29/7397 , H01L29/0847
摘要： In a semiconductor device having a substrate, a p-type semiconductor layer, an n-type channel well region, a p-type lightly doped source region, and a source electrode formed on the substrate in this order, a p-type heavily-doped source region, an impurity concentration of which is higher than that of the lightly-doped source region, is formed in a surface region of the lightly-doped source region. The source electrode is formed to contact the heavily-doped source region. As a result, a punch through phenomenon between the p-type source region and the p-type semiconductor layer through the n-type channel well region can be prevented without increasing in the On resistance of the semiconductor device.
摘要翻译：在具有衬底，p型半导体层，n型沟道阱区，p型轻掺杂源极区域和在该衬底上形成的源极电极的半导体器件中，在轻掺杂源极区域的表面区域中形成杂质浓度高于轻掺杂源极区域的掺杂源极区域。源电极形成为接触重掺杂源极区。结果，可以在不增加半导体器件的导通电阻的情况下，防止通过n型沟道阱区域的p型源极区域和p型半导体层之间的穿透现象。

4. 发明授权

US5747851A Semiconductor device with reduced breakdown voltage between the gate electrode and semiconductor surface 失效
标题翻译：在栅电极和半导体表面之间具有高击穿电压的半导体器件
公开(公告)号：US5747851A
公开(公告)日：1998-05-05
申请号：US723804
申请日：1996-09-30
申请人： Yutaka Tomatsu , Mitsuhiro Kataoka
发明人： Yutaka Tomatsu , Mitsuhiro Kataoka
IPC分类号： H01L21/316 , H01L29/06 , H01L29/739 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062
CPC分类号： H01L29/0696 , H01L29/7397 , H01L29/7813
摘要： A concave type DMOS transistor structure can attain improvement in a life-time of a gate insulating film. An initial groove portion is thermally oxidized with a silicon nitride film as a mask. A LOCOS oxide film is formed by this oxidation; concurrently, a U-groove is formed due to the erosion of the surface of an epitaxial layer by the LOCOS oxide film, and moreover the configuration of the groove is fixed. At this time, an inlet corner portion of the initial groove formed by chemical dry etching remains as a curving portion at a sidewall surface of the groove. Thereafter, a gate insulating film is formed, but thickness of the gate insulating film is controlled to be thicker on a groove inlet-portion side than on a groove bottom-portion side, with the curving portion as the boundary.
摘要翻译：凹型DMOS晶体管结构可以在栅绝缘膜的使用寿命内得到改善。初始槽部用氮化硅膜作为掩模进行热氧化。通过氧化形成LOCOS氧化膜; 同时，由于通过LOCOS氧化膜对外延层的表面的侵蚀，形成U形槽，此外，槽的结构是固定的。此时，通过化学干蚀刻形成的初始凹槽的入口角部分在凹槽的侧壁表面保持为弯曲部分。此后，形成栅极绝缘膜，但是栅极绝缘膜的厚度在凹槽入口部分侧比凹槽底部侧更厚，其中弯曲部分作为边界。

5. 发明授权

US5698880A Semiconductor device having a groove with a curved part formed on its side surface 失效
标题翻译：半导体器件具有在其侧表面上形成有弯曲部分的凹槽
公开(公告)号：US5698880A
公开(公告)日：1997-12-16
申请号：US539380
申请日：1995-10-05
申请人： Shigeki Takahashi , Mitsuhiro Kataoka , Tsuyoshi Yamamoto , Yuuichi Takeuchi , Norihito Tokura
发明人： Shigeki Takahashi , Mitsuhiro Kataoka , Tsuyoshi Yamamoto , Yuuichi Takeuchi , Norihito Tokura
IPC分类号： H01L21/336 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： Y02E10/50
摘要： A manufacturing method for a semiconductor device, which can attain a low ion voltage in a manufacturing method for a semiconductor device involving a process for forming a groove by etching prior to selective oxidation, selectively oxidizing a region including the groove and thereby making a channel part of the groove, is disclosed. A groove part is thermally oxidized by using a silicon nitride film as a mask. A LOCOS oxide film is formed by this thermal oxidation, and concurrently a U-groove is formed on the surface of an n.sup.- -type epitaxial layer eroded by the LOCOS oxide film, and the shape of the U-groove is fixed. A curve part formed during a chemical dry etching process remains as a curve part on the side surface of the U-groove. Then, an n.sup.+ -type source layer is formed by means of thermal diffusion to a junction thickness of 0.5 to 1 .mu.m, and a channel is set up as well. The junction depth obtained by this thermal diffusion is set up more deeply than the curve part which is formed during the above etching and remains on the side surface of the U-groove after the above selective thermal oxidation.
摘要翻译：一种用于半导体器件的制造方法的半导体器件的制造方法，其包括在选择性氧化之前通过蚀刻形成沟槽的工艺的半导体器件的制造方法，选择性地氧化包括沟槽的区域，从而形成沟道部分的凹槽。通过使用氮化硅膜作为掩模将槽部热氧化。通过该热氧化形成LOCOS氧化物膜，并且在由LOCOS氧化物膜侵蚀的n型外延层的表面上形成U形槽，并且U形槽的形状被固定。在化学干蚀刻过程中形成的曲线部分在U形槽的侧表面上保持为曲线部分。然后，通过热扩散形成0.5±1μm的结合厚度的n +型源极层，并且还设置沟道。通过该热扩散获得的结深度比在上述蚀刻期间形成的曲线部分更深地设置，并且在上述选择性热氧化之后保留在U形槽的侧表面上。

6. 发明授权

US08970088B2 Thermionic converter 有权
标题翻译：热电转换器
公开(公告)号：US08970088B2
公开(公告)日：2015-03-03
申请号：US12964145
申请日：2010-12-09
申请人： Yuji Kimura , Susumu Sobue , Mitsuhiro Kataoka , Eiichi Okuno , Shoichi Kawai
发明人： Yuji Kimura , Susumu Sobue , Mitsuhiro Kataoka , Eiichi Okuno , Shoichi Kawai
IPC分类号： H02N10/00 , H01J45/00
CPC分类号： H01J45/00
摘要： A thermionic converter for converting thermal energy to electrical energy includes an emitter and a collector. The emitter emits thermionic electrons upon receipt of heat from a heat source. The emitter is made of a first semiconductor material to which a first semiconductor impurity is doped with a first concentration. The collector is spaced and opposite to the emitter to receive the thermionic electrons emitted from the emitter so that the thermal energy is converted to electrical energy. The collector is made of a second semiconductor material to which a second semiconductor impurity is doped with a second concentration less than the first concentration.
摘要翻译：用于将热能转换为电能的热离子转换器包括发射极和集电极。当从热源接收到热量时，发射器发射热离子电子。发射极由第一半导体材料制成，第一半导体杂质掺杂有第一浓度。收集器与发射器间隔开并相对，以接收从发射极发射的热离子电子，从而将热能转换成电能。集电体由第二半导体材料制成，第二半导体杂质掺杂有第二浓度小于第一浓度的第二浓度。

7. 发明授权

US07164154B2 Gate wiring layout for silicon-carbide-based junction field effect transistor 有权
标题翻译：基于碳化硅的结型场效应晶体管的栅极布线布局
公开(公告)号：US07164154B2
公开(公告)日：2007-01-16
申请号：US10995566
申请日：2004-11-24
申请人： Rajesh Kumar , Yuichi Takeuchi , Mitsuhiro Kataoka , Suhail Rashid Jeremy , Andrei Mihaila , Florin Udrea
发明人： Rajesh Kumar , Yuichi Takeuchi , Mitsuhiro Kataoka , Suhail Rashid Jeremy , Andrei Mihaila , Florin Udrea
IPC分类号： H01L29/15
CPC分类号： H01L29/8083 , H01L29/1608
摘要： A silicon carbide semiconductor device includes: a semiconductor substrate including first and second gate layers, a channel layer, a source layer, and a trench; a gate wiring having a first portion and a plurality of second portions; and a source wiring having a third portion and a plurality of fourth portions. The trench extends in a predetermined extending direction. The first portion connects to the first gate layer in the trench, and extends to the extending direction. The second portions protrude perpendicularly to be a comb shape. The third portion extends to the extending direction. The fourth portions protrude perpendicularly to be a comb shape, and electrically connect to the source layer. Each of the second portions connects to the second gate layer through a contact hole.
摘要翻译：碳化硅半导体器件包括：包括第一和第二栅极层，沟道层，源极层和沟槽的半导体衬底; 栅极布线，具有第一部分和多个第二部分; 以及具有第三部分和多个第四部分的源极布线。沟槽沿预定的延伸方向延伸。第一部分连接到沟槽中的第一栅极层，并延伸到延伸方向。第二部分垂直突出成为梳形。第三部分延伸到延伸方向。第四部分垂直突出成梳状，并且电连接到源层。每个第二部分通过接触孔连接到第二栅极层。

8. 发明授权

US07821013B2 Silicon carbide semiconductor device 有权
标题翻译：碳化硅半导体器件
公开(公告)号：US07821013B2
公开(公告)日：2010-10-26
申请号：US11501777
申请日：2006-08-10
申请人： Rajesh Kumar , Yuichi Takeuchi , Mitsuhiro Kataoka , Suhail Rashid Jeremy , Andrei Mihaila , Florin Udrea
发明人： Rajesh Kumar , Yuichi Takeuchi , Mitsuhiro Kataoka , Suhail Rashid Jeremy , Andrei Mihaila , Florin Udrea
IPC分类号： H01L29/12 , H01L29/41
CPC分类号： H01L29/8083 , H01L29/1608
摘要： A silicon carbide semiconductor device includes: a semiconductor substrate including first and second gate layers, a channel layer, a source layer, and a trench; a gate wiring having a first portion and a plurality of second portions; and a source wiring having a third portion and a plurality of fourth portions. The trench extends in a predetermined extending direction. The first portion connects to the first gate layer in the trench, and extends to the extending direction. The second portions protrude perpendicularly to be a comb shape. The third portion extends to the extending direction. The fourth portions protrude perpendicularly to be a comb shape, and electrically connect to the source layer. Each of the second portions connects to the second gate layer through a contact hole.
摘要翻译：碳化硅半导体器件包括：包括第一和第二栅极层，沟道层，源极层和沟槽的半导体衬底; 栅极布线，具有第一部分和多个第二部分; 以及具有第三部分和多个第四部分的源极布线。沟槽沿预定的延伸方向延伸。第一部分连接到沟槽中的第一栅极层，并延伸到延伸方向。第二部分垂直突出成为梳形。第三部分延伸到延伸方向。第四部分垂直突出成梳状，并且电连接到源层。每个第二部分通过接触孔连接到第二栅极层。

9. 发明申请

US20060087194A1 Motor using rectangular waveform conductor 审中-公开
标题翻译：电机采用矩形波形导体
公开(公告)号：US20060087194A1
公开(公告)日：2006-04-27
申请号：US10540269
申请日：2005-03-10
申请人： Mitsuhiro Kataoka
发明人： Mitsuhiro Kataoka
IPC分类号： H02K41/00 , H02K21/12 , H02K21/00
CPC分类号： H02K41/03 , E05F15/60 , H02K3/26 , H02K21/24
摘要： To provide a compact, light and simple linear or rotary motor driven by direct-current electric power at a low manufacturing cost for use of house fittings, carrying devices, electronic devices, and home electric appliances, a linear magnetic pole row (2) or an annular magnetic pole row (4) in which N and S poles are alternately arranged is structured with permanent magnets as a movable side electromagnetic member, two sets of coreless-type rectangular wave wires are provided as a fixed side electromagnetic member, every time when the magnetic pole row moves by one half pitch, the electricity application is switched from one of the two sets of wave wires to the other.
摘要翻译：为了提供以低制造成本驱动的紧凑，轻便和简单的直线或旋转电机，用于房屋配件，承载装置，电子设备和家用电器的使用，线性磁极列（2）或以永磁体作为可移动侧电磁构件，以N和S极交替排列的环形磁极列（4）构成两组无芯型矩形波导线作为固定侧电磁构件，磁极列移动一半间距，将电力应用从两组波形线中的一组切换到另一组。

10. 发明授权

US6015737A Production method of a vertical type MOSFET 失效
标题翻译：垂直型MOSFET的制造方法
公开(公告)号：US6015737A
公开(公告)日：2000-01-18
申请号：US515176
申请日：1995-08-15
申请人： Norihito Tokura , Shigeki Takahashi , Tsuyoshi Yamamoto , Mitsuhiro Kataoka
发明人： Norihito Tokura , Shigeki Takahashi , Tsuyoshi Yamamoto , Mitsuhiro Kataoka
IPC分类号： H01L21/336 , H01L29/04 , H01L29/06 , H01L29/423 , H01L29/78
CPC分类号： H01L29/045 , H01L29/0696 , H01L29/7813 , H01L29/4236
摘要： A vertical type power MOSFET remarkably reduces its ON-resistance per area. A substantial groove formation in which a gate structure is constituted is performed beforehand utilizing the LOCOS method before the formation of a p-type base layer and an n.sup.+ -type source layer. The p-type base layer and the n.sup.+ -type source layer are then formed by double diffusion in a manner of self-alignment with respect to a LOCOS oxide film, simultaneously with which channels are set at sidewall portions of the LOCOS oxide film. Thereafter the LOCOS oxide film is removed to provide a U-groove so as to constitute the gate structure. Namely, the channels are set by the double diffusion of the manner of self-alignment with respect to the LOCOS oxide film, so that the channels, which are set at the sidewall portions at both sides of the groove, provide a structure of exact bilateral symmetry, there is no positional deviation of the U-groove with respect to the base layer end, and the length of the bottom face of the U-groove can be made minimally short. Therefore, the unit cell size is greatly reduced, and the ON-resistance per area is greatly decreased.
摘要翻译：垂直型功率MOSFET可显着降低每个区域的导通电阻。在形成p型基极层和n +型源极层之前，利用LOCOS方法预先利用构成栅极结构的实质的槽形成。然后通过相对于LOCOS氧化物膜的自对准的双扩散形成p型基极层和n +型源极层，同时将通道设置在LOCOS氧化物膜的侧壁部分。此后，去除LOCOS氧化物膜以提供U形槽以构成栅极结构。即，通过相对于LOCOS氧化膜的自对准方式的双扩散来设定通道，使得设置在凹槽两侧的侧壁部分处的通道提供精确双边的结构 U形槽相对于基底层端部没有位置偏离，U槽的底面的长度最短。因此，单元电池尺寸大大降低，并且每个面积的导通电阻大大降低。

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