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1. 发明授权

US4567172A 6.alpha.-Methylprednisolone derivatives 失效
标题翻译： 6α-甲基强的松龙衍生物
公开(公告)号：US4567172A
公开(公告)日：1986-01-28
申请号：US498636
申请日：1983-05-27
申请人： Yoshiaki Kamano , Saburo Sugai , Tokuji Okazaki , Seiichiro Yoshida , Sanya Akaboshi
发明人： Yoshiaki Kamano , Saburo Sugai , Tokuji Okazaki , Seiichiro Yoshida , Sanya Akaboshi
IPC分类号： C07J5/00 , C07J21/00 , C07J31/00 , A61K31/56
CPC分类号： C07J21/00 , C07J31/006 , C07J5/0053
摘要： A 6.alpha.-methylprednisolone derivative of the general formula: ##STR1## wherein R.sup.1 is a hydrogen atom or stands for the grouping ##STR2## where R.sup.3 is a straight or once-branched chain C.sub.1-4 alkyl group, a phenyl group or a lower alkoxy- or alkylthio-methyl group, and R.sup.2 is a straight or once-branched chain C.sub.1-4 alkyl group, a phenyl group or a lower alkoxy- or alkylthio-methyl group, with the proviso that when R.sup.2 is ethyl group, R.sup.1 should not be a hydrogen atom or R.sup.3 should not be ethyl group. This compound exhibits a strong local antiinflammatory effect and is, therefore, useful as a harmless external antiinflammatory drug for various dermal disorders and also as an antiallergic drug for treating asthma and the like allergic diseases.
摘要翻译：一种具有下列通式的6α-甲基泼尼松龙衍生物：其中R 1是氢原子或代表基团，其中R 3是直链或一次支链C 1-4烷基，苯基或低级烷氧基 - 或烷硫基 - 甲基，R 2为直链或单支链C 1-4烷基，苯基或低级烷氧基 - 或烷硫基 - 甲基，条件是当R 2为乙基 R1不宜为氢原子，R3不宜为乙基。该化合物显示出强烈的局部抗炎作用，因此可用作各种皮肤病的无害外用抗炎药物，也可用作治疗哮喘等过敏性疾病的抗过敏药物。

2. 发明申请

US20090098834A1 FREQUENCY SYNTHESIZER, RADIO COMMUNICATION SYSTEM, AND SEMICONDUCTOR DEVICE 审中-公开
标题翻译：频率合成器，无线电通信系统和半导体器件
公开(公告)号：US20090098834A1
公开(公告)日：2009-04-16
申请号：US12282045
申请日：2007-03-06
申请人： Seiichiro Yoshida , Joji Hayashi
发明人： Seiichiro Yoshida , Joji Hayashi
IPC分类号： H04B1/40
CPC分类号： H04L27/12 , H03C3/0925 , H03C3/0933 , H03L7/1976
摘要： In transmission frequency modulation in radio communication, correspondences to multiple-value frequency modulation having plural-bits transmission data are realized while suppressing an increase in the circuit area. When performing transmission frequency modulation in radio communication, response data of a digital filter are calculated by a logic circuit that is embedded in a transmission modulator. Since a change amount in the division number is calculated by the logic circuit, a ROM for storing the response data is dispensed with, and thereby an increase in the circuit area can be suppressed when the transmission modulator corresponds to variations in the frequency of a reference signal or to multiple-value frequency modulation having plural-bits transmission data. Further, bandwidth narrowing of a transmission signal spectrum is realized by performing the transmission frequency modulation with dividing the process thereof into plural steps using a timing synchronized with a clock.
摘要翻译：在无线通信中的发送频率调制中，与抑制电路面积的增加同时实现与具有多位发送数据的多值频率调制对应。当在无线电通信中执行传输频率调制时，数字滤波器的响应数据由嵌入在传输调制器中的逻辑电路计算。由于通过逻辑电路计算分割数的变化量，所以省略了用于存储响应数据的ROM，从而当传输调制器对应于参考频率的变化时可以抑制电路面积的增加信号或具有多位传输数据的多值频率调制。此外，通过使用与时钟同步的定时将其处理分成多个步骤来实现发送频率调制来实现发送信号频谱的带宽窄化。

3. 发明申请

US20100260242A1 TIME DIGITAL CONVERTER, DIGITAL PLL FREQUENCY SYNTHESIZER, TRANSCEIVER, AND RECEIVER 审中-公开
标题翻译：数字数字转换器，数字PLL频率合成器，收发器和接收器
公开(公告)号：US20100260242A1
公开(公告)日：2010-10-14
申请号：US12746673
申请日：2009-02-16
申请人： Katsuaki Abe , Akihiro Sawada , Seiichiro Yoshida
发明人： Katsuaki Abe , Akihiro Sawada , Seiichiro Yoshida
IPC分类号： H03M1/34 , H03L7/00 , H04B1/38 , H04L27/00
CPC分类号： H03K5/13 , H03L7/0812
摘要： A variable delay circuit (101) generates a plurality of delay signals (D(1), D(2), . . . , D(n)). An output holding circuit (102) receives the plurality of delay signals (D(1), D(2), . . . , D(n)) in synchronization with a transition of a reference signal (Sref). A selector (104) provides an input signal (Sin) to the variable delay circuit (101) in a normal mode, and provides one of the plurality of delay signals (D(1), D(2), . . . , D(n)) to the variable delay circuit (101) in a calibration mode. A frequency measurement circuit (105) counts the number of transitions of one of the plurality of delay signals (D(1), D(2), . . . , D(n)) during a predetermined frequency measurement period. In the calibration mode, a delay-amount calibration circuit (106) adjusts a delay time of the variable delay circuit (101) so that the number of transitions counted by the frequency measurement circuit (105) approaches a target value corresponding to a frequency of the input signal (Sin).
摘要翻译：可变延迟电路（101）产生多个延迟信号（D（1），D（2），...，D（n））。输出保持电路（102）与参考信号（Sref）的转换同步地接收多个延迟信号（D（1），D（2），...，D（n））。选择器（104）以正常模式向可变延迟电路（101）提供输入信号（Sin），并提供多个延迟信号（D（1），D（2），...，D （n））到可变延迟电路（101）。频率测量电路（105）在预定的频率测量周期期间对多个延迟信号（D（1），D（2），...，D（n））之一的转换次数进行计数。在校准模式中，延迟量校准电路（106）调整可变延迟电路（101）的延迟时间，使得由频率测量电路（105）计数的转换次数接近对应于频率测量电路输入信号（Sin）。

4. 发明授权

US07714668B2 Phase locked loop circuit and wireless communication system 失效
标题翻译：锁相环电路和无线通信系统
公开(公告)号：US07714668B2
公开(公告)日：2010-05-11
申请号：US12194836
申请日：2008-08-20
申请人： Seiichiro Yoshida , Akihiro Sawada
发明人： Seiichiro Yoshida , Akihiro Sawada
IPC分类号： H03L7/087
CPC分类号： H03L7/099 , H03L7/087 , H03L7/091 , H03L7/10 , H03L2207/06
摘要： In a PLL circuit including a VCO having a plurality of oscillation frequency bands, a TDC circuit calculates a phase difference between a predetermined reference signal from a fixed frequency divider and a PLL frequency-divided signal from a variable frequency divider. The TDC circuit detects the amount of time by which the phase of the PLL frequency-divided signal leads or lags with respect to that of the reference signal in one cycle of the reference signal, thereby detecting which of the signals has a higher frequency and which has a lower frequency. Therefore, for each oscillation frequency band, the frequency comparison is completed in one cycle of the reference signal, allowing an oscillation frequency band selection circuit to detect an optimum oscillation frequency band corresponding to a predetermined PLL output frequency in a short time.
摘要翻译：在包括具有多个振荡频带的VCO的PLL电路中，TDC电路计算来自固定分频器的预定参考信号与来自可变分频器的PLL分频信号之间的相位差。 TDC电路在参考信号的一个周期中检测PLL分频信号的相位相对于参考信号的相位导致或滞后的时间量，从而检测哪个信号具有较高的频率，以及哪个频率较低。因此，对于每个振荡频带，在参考信号的一个周期内完成频率比较，允许振荡频带选择电路在短时间内检测对应于预定PLL输出频率的最佳振荡频带。

5. 发明申请

US20120049912A1 DIGITAL PHASE DIFFERENCE DETECTOR AND FREQUENCY SYNTHESIZER INCLUDING THE SAME 审中-公开
标题翻译：数字相位差分检测器和频率合成器，包括它们
公开(公告)号：US20120049912A1
公开(公告)日：2012-03-01
申请号：US13289707
申请日：2011-11-04
申请人： Seiichiro Yoshida , Atsushi Ohara
发明人： Seiichiro Yoshida , Atsushi Ohara
IPC分类号： H03L7/08
CPC分类号： H03K5/26 , H03K5/159 , H03L7/085 , H03L2207/50
摘要： A digital phase difference detector detects a phase difference between first and second signals. A delay circuit cumulatively delays the first signal. A flip flop group latches the signals. An edge detector detects a first phase difference between a rise of the first signal and either one of a rise or a fall of the second signal, and a second phase difference between a fall of the first signal and either one of the rise or the fall of the second signal. A memory circuit stores the phase differences. A normalization circuit computes a cycle of the first signal from a difference between previous first and second phase differences stored in the memory circuit and a difference between the first and second phase differences which are currently detected by the edge detector to normalize the phase difference between the first and second signals with reference to the cycle.
摘要翻译：数字相位差检测器检测第一和第二信号之间的相位差。延迟电路累积地延迟第一信号。触发器组锁定信号。边缘检测器检测第一信号的上升与第二信号的上升或下降中的任一个之间的第一相位差，以及第一信号的下降与上升或下降中的任一个之间的第二相位差的第二信号。存储电路存储相位差。归一化电路根据存储在存储器电路中的先前第一和第二相位差之间的差计算第一信号的周期，并且由边缘检测器当前检测到的第一和第二相位差之间的差异来归一化第参考周期的第一和第二信号。

6. 发明申请

US20090102570A1 PHASE LOCKED LOOP CIRCUIT AND WIRELESS COMMUNICATION SYSTEM 失效
标题翻译：相位锁定环路和无线通信系统
公开(公告)号：US20090102570A1
公开(公告)日：2009-04-23
申请号：US12194836
申请日：2008-08-20
申请人： Seiichiro Yoshida , Akihiro Sawada
发明人： Seiichiro Yoshida , Akihiro Sawada
IPC分类号： H03L7/099
CPC分类号： H03L7/099 , H03L7/087 , H03L7/091 , H03L7/10 , H03L2207/06
摘要： In a PLL circuit including a VCO having a plurality of oscillation frequency bands, a TDC circuit calculates a phase difference between a predetermined reference signal from a fixed frequency divider and a PLL frequency-divided signal from a variable frequency divider on a rising edge of the reference signal and then calculates a phase difference between the reference signal and the PLL frequency-divided signal on the next rising edge of the reference signal in the same manner. From information on the two calculated phase differences, the TDC circuit detects the amount of time by which the phase of the PLL frequency-divided signal leads or lags with respect to that of the reference signal in one cycle of the reference signal, thereby detecting which of the signals, the reference signal or the PLL frequency-divided signal, has a higher frequency and which has a lower frequency. Therefore, for each oscillation frequency band, the frequency comparison is completed in one cycle of the reference signal, allowing an oscillation frequency band selection circuit to detect an optimum oscillation frequency band corresponding to a predetermined PLL output frequency in a short time.
摘要翻译：在包括具有多个振荡频带的VCO的PLL电路中，TDC电路计算来自固定分频器的预定参考信号与来自可变分频器的PLL分频信号之间的相位差，参考信号，然后以相同的方式在参考信号的下一个上升沿计算参考信号和PLL分频信号之间的相位差。根据两个计算出的相位差的信息，TDC电路检测PLL分频信号的相位在参考信号的一个周期中相对于参考信号的相位导致或滞后的时间量，从而检测哪个的信号，参考信号或PLL分频信号具有较高的频率，频率较低。因此，对于每个振荡频带，在参考信号的一个周期内完成频率比较，允许振荡频带选择电路在短时间内检测对应于预定PLL输出频率的最佳振荡频带。

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