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1. 发明申请

US20150145015A1 THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：三维半导体存储器件
公开(公告)号：US20150145015A1
公开(公告)日：2015-05-28
申请号：US14519713
申请日：2014-10-21
申请人： Yoocheol Shin , Hongsoo Kim , Jaesung Sim
发明人： Yoocheol Shin , Hongsoo Kim , Jaesung Sim
IPC分类号： H01L27/115
CPC分类号： H01L27/11556 , G11C16/0483 , H01L27/11531 , H01L27/11548 , H01L27/11573 , H01L27/11575 , H01L27/11582
摘要： A three-dimensional semiconductor memory device includes stacked structures, vertical semiconductor patterns, common source regions, and well pickup regions. The stacked structures are disposed on a semiconductor layer of a first conductivity type. Each stacked structure includes electrodes vertically stacked on each other and is extended in a first direction. The vertical semiconductor patterns penetrate the stacked structures. The common source regions of a second conductivity type are disposed in the semiconductor layer. At least one common source region is disposed between two adjacent stacked structures. The at least one common source region is extended in the first direction. The well pickup regions of the first conductivity type are disposed in the semiconductor layer. At least one well pickup region is adjacent to both ends of at least one stacked structure.
摘要翻译：三维半导体存储器件包括堆叠结构，垂直半导体图案，公共源极区域和阱拾取区域。堆叠结构设置在第一导电类型的半导体层上。每个堆叠结构包括彼此垂直堆叠并沿第一方向延伸的电极。垂直半导体图案穿透层叠结构。第二导电类型的公共源极区域设置在半导体层中。在两个相邻的堆叠结构之间设置至少一个公共源区。所述至少一个公共源区域沿第一方向延伸。第一导电类型的阱拾取区域设置在半导体层中。至少一个阱拾取区域与至少一个堆叠结构的两端相邻。

2. 发明授权

US09287167B2 Vertical type memory device 有权
标题翻译：垂直式存储装置
公开(公告)号：US09287167B2
公开(公告)日：2016-03-15
申请号：US14200002
申请日：2014-03-06
申请人： Kwang Soo Seol , Seong Soon Cho , Byungjoo Go , Hongsoo Kim
发明人： Kwang Soo Seol , Seong Soon Cho , Byungjoo Go , Hongsoo Kim
IPC分类号： G11C11/34 , G11C16/04 , H01L21/768 , H01L29/423 , H01L29/66 , H01L29/788 , H01L29/792 , H01L27/115
CPC分类号： H01L21/76877 , H01L27/11519 , H01L27/11556 , H01L27/11565 , H01L27/11582 , H01L29/42332 , H01L29/66825 , H01L29/7889 , H01L29/7926
摘要： A method of fabricating a semiconductor device, comprising: forming a plurality of memory cell strings; coupling an interconnection to at least two of the memory cell strings; and coupling a bitline to the interconnection. The interconnection includes a body extending along a first direction and a protrusion protruding from the body along a second direction.
摘要翻译：一种制造半导体器件的方法，包括：形成多个存储单元串; 将互连耦合到所述存储单元串中的至少两个; 并将位线耦合到互连。互连包括沿着第一方向延伸的主体和沿着第二方向从主体突出的突起。

3. 发明申请

US20180026049A1 SEMICONDUCTOR MEMORY DEVICES HAVING VERTICAL PILLARS THAT ARE ELECTRICALLY CONNECTED TO LOWER CONTACTS 审中-公开
公开(公告)号：US20180026049A1
公开(公告)日：2018-01-25
申请号：US15706861
申请日：2017-09-18
申请人： TaeHee Lee , Kyoung-Hoon Kim , Hongsoo Kim
发明人： TaeHee Lee , Kyoung-Hoon Kim , Hongsoo Kim
IPC分类号： H01L27/11582
CPC分类号： H01L27/11582 , H01L28/00
摘要： A semiconductor memory device may include an electrode structure including a selection line on a substrate and word lines between the substrate and the selection line, vertical pillars penetrating the electrode structure and being connected to the substrate, sub-interconnections and bit lines sequentially stacked on and electrically connected to the vertical pillars, and lower contacts connecting the vertical pillars to the sub-interconnections. The selection line may include a plurality of selection lines separated from each other in a first direction by an insulating separation layer, and central axes of the lower contacts connected in common to one of the sub-interconnections may be shifted, in a second direction across the first direction and parallel to a top surface of the substrate, from central axes of the vertical pillars thereunder.

4. 发明授权

US09184174B2 Semiconductor devices and methods of fabricating semiconductor devices 有权
标题翻译：半导体器件和制造半导体器件的方法
公开(公告)号：US09184174B2
公开(公告)日：2015-11-10
申请号：US14155649
申请日：2014-01-15
申请人： Jang-Gn Yun , Hongsoo Kim , Aaron Park , Hoosung Cho
发明人： Jang-Gn Yun , Hongsoo Kim , Aaron Park , Hoosung Cho
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L27/115
CPC分类号： H01L27/1157 , H01L27/11575 , H01L27/11582 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices are provided. A semiconductor device may include a substrate and a plurality of lines on the substrate. The semiconductor device may include a dielectric layer on the substrate and adjacent the plurality of lines. The semiconductor device may include a connection element in the dielectric layer. In some embodiments, the semiconductor device may include a plurality of contacts on the connection element, and a conductive interconnection on one of the plurality of contacts that are on the connection element and on a contact that is spaced apart from the connection element.
摘要翻译：提供半导体器件。半导体器件可以包括衬底和衬底上的多条线。半导体器件可以包括在衬底上并与多条线相邻的电介质层。该半导体器件可以包括介电层中的连接元件。在一些实施例中，半导体器件可以包括连接元件上的多个触点，以及在连接元件上的多个触点中的一个触点上以及与连接元件间隔开的触点上的导电互连。

5. 发明授权

US09768190B2 Semiconductor memory devices having vertical pillars that are electrically connected to lower contacts 有权
公开(公告)号：US09768190B2
公开(公告)日：2017-09-19
申请号：US14963280
申请日：2015-12-09
申请人： TaeHee Lee , Kyoung-Hoon Kim , Hongsoo Kim
发明人： TaeHee Lee , Kyoung-Hoon Kim , Hongsoo Kim
IPC分类号： H01L29/792 , H01L27/11582
CPC分类号： H01L27/11582 , H01L28/00
摘要： A semiconductor memory device may include an electrode structure including a selection line on a substrate and word lines between the substrate and the selection line, vertical pillars penetrating the electrode structure and being connected to the substrate, sub-interconnections and bit lines sequentially stacked on and electrically connected to the vertical pillars, and lower contacts connecting the vertical pillars to the sub-interconnections. The selection line may include a plurality of selection lines separated from each other in a first direction by an insulating separation layer, and central axes of the lower contacts connected in common to one of the sub-interconnections may be shifted, in a second direction across the first direction and parallel to a top surface of the substrate, from central axes of the vertical pillars thereunder.

6. 发明申请

US20140197542A1 SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING SEMICONDUCTOR DEVICES 有权
标题翻译：半导体器件和制造半导体器件的方法
公开(公告)号：US20140197542A1
公开(公告)日：2014-07-17
申请号：US14155649
申请日：2014-01-15
申请人： Jang-Gn Yun , Hongsoo Kim , Aaron Park , Hoosung Cho
发明人： Jang-Gn Yun , Hongsoo Kim , Aaron Park , Hoosung Cho
IPC分类号： H01L23/528
CPC分类号： H01L27/1157 , H01L27/11575 , H01L27/11582 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices are provided. A semiconductor device may include a substrate and a plurality of lines on the substrate. The semiconductor device may include a dielectric layer on the substrate and adjacent the plurality of lines. The semiconductor device may include a connection element in the dielectric layer. In some embodiments, the semiconductor device may include a plurality of contacts on the connection element, and a conductive interconnection on one of the plurality of contacts that are on the connection element and on a contact that is spaced apart from the connection element.
摘要翻译：提供半导体器件。半导体器件可以包括衬底和衬底上的多条线。半导体器件可以包括在衬底上并与多条线相邻的电介质层。该半导体器件可以包括介电层中的连接元件。在一些实施例中，半导体器件可以包括连接元件上的多个触点，以及在连接元件上的多个触点中的一个触点上以及与连接元件间隔开的触点上的导电互连。

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