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1. 发明授权

US08239843B2 Value predictable variable scoping for speculative automatic parallelization with transactional memory 有权
标题翻译：值可预测的变量范围，用于事务性内存的投机自动并行化
公开(公告)号：US08239843B2
公开(公告)日：2012-08-07
申请号：US12046365
申请日：2008-03-11
申请人： Yonghong Song , Xiangyun Kong , Spiros Kalogeropulos , Partha P. Tirumalai
发明人： Yonghong Song , Xiangyun Kong , Spiros Kalogeropulos , Partha P. Tirumalai
IPC分类号： G06F9/45
CPC分类号： G06F8/456
摘要： Parallelize a computer program by scoping program variables at compile time and inserting code into the program. Identify as value predictable variables, variables that are: defined only once in a loop of the program; not defined in any inner loop of the loop; and used in the loop. Optionally also: identify a code block in the program that contains a variable assignment, and then traverse a path backwards from the block through a control flow graph of the program. Name in a set all blocks along the path until a loop header block. For each block in the set, determine program blocks that logically succeed the block and are not in the first set. Identify all paths between the block and the determined blocks as failure paths, and insert code into the failure paths. When executed at run time of the program, the inserted code fails the corresponding path.
摘要翻译：通过在编译时对程序变量进行范围并将代码插入程序来并行化计算机程序。识别为值可预测变量，变量是：在程序循环中仅定义一次; 没有在循环的任何内循环中定义; 并在循环中使用。还可以：识别包含变量赋值的程序中的代码块，然后通过程序的控制流程图从块向后移动一个路径。命名一个路径中的所有块，直到循环头块。对于集合中的每个块，确定在块上逻辑成功并且不在第一组中的程序块。将块和确定的块之间的所有路径标识为故障路径，并将代码插入故障路径。当在程序的运行时执行时，插入的代码失败相应的路径。

2. 发明申请

US20090217253A1 COMPILER FRAMEWORK FOR SPECULATIVE AUTOMATIC PARALLELIZATION WITH TRANSACTIONAL MEMORY 有权
标题翻译：用于具有交互式存储器的自动自动并行化的编译器框架
公开(公告)号：US20090217253A1
公开(公告)日：2009-08-27
申请号：US12035828
申请日：2008-02-22
申请人： Yonghong Song , Xiangyun Kong , Spiros Kalogeropulos , Partha P. Tirumalai
发明人： Yonghong Song , Xiangyun Kong , Spiros Kalogeropulos , Partha P. Tirumalai
IPC分类号： G06F9/45
CPC分类号： G06F9/3863 , G06F8/456 , G06F9/3842 , G06F9/3851
摘要： A computer program is speculatively parallelized with transactional memory by scoping program variables at compile time, and inserting code into the program at compile time. Determinations of the scoping can be based on whether scalar variables being scoped are involved in inter-loop non-reduction data dependencies, are used outside loops in which they were defined, and at what point in a loop a scalar variable is defined. The inserted code can include instructions for execution at a run time of the program to determine loop boundaries of the program, and issue checkpoint instructions and commit instructions that encompass transaction regions in the program. A transaction region can include an original function of the program and a spin-waiting loop with a non-transactional load, wherein the spin-waiting loop is configured to wait for a previous thread to commit before the current transaction commits.
摘要翻译：计算机程序通过在编译时对程序变量进行范围划分，并在编译时将代码插入到程序中，通过事务性存储器推测并行化。范围界定的确定可以基于范围变量是否涉及到循环中的非还原数据依赖关系，它们被定义在外部循环中，以及在循环中什么时候定义标量变量。插入的代码可以包括用于在程序运行时执行的指令以确定程序的循环边界，以及发出检查点指令并提交包含程序中的事务区域的指令。事务区域可以包括程序的原始功能和具有非事务负载的自转等待循环，其中，所述旋转等待循环被配置为在当前事务提交之前等待先前线程提交。

3. 发明授权

US08151252B2 Compiler framework for speculative automatic parallelization with transactional memory 有权
标题翻译：用于使用事务性内存进行投机自动并行化的编译器框架
公开(公告)号：US08151252B2
公开(公告)日：2012-04-03
申请号：US12035828
申请日：2008-02-22
申请人： Yonghong Song , Xiangyun Kong , Spiros Kalogeropulos , Partha P. Tirumalai
发明人： Yonghong Song , Xiangyun Kong , Spiros Kalogeropulos , Partha P. Tirumalai
IPC分类号： G06F9/45
CPC分类号： G06F9/3863 , G06F8/456 , G06F9/3842 , G06F9/3851
摘要： A computer program is speculatively parallelized with transactional memory by scoping program variables at compile time, and inserting code into the program at compile time. Determinations of the scoping can be based on whether scalar variables being scoped are involved in inter-loop non-reduction data dependencies, are used outside loops in which they were defined, and at what point in a loop a scalar variable is defined. The inserted code can include instructions for execution at a run time of the program to determine loop boundaries of the program, and issue checkpoint instructions and commit instructions that encompass transaction regions in the program. A transaction region can include an original function of the program and a spin-waiting loop with a non-transactional load, wherein the spin-waiting loop is configured to wait for a previous thread to commit before the current transaction commits.
摘要翻译：计算机程序通过在编译时对程序变量进行范围划分，并在编译时将代码插入到程序中，通过事务性存储器推测并行化。范围界定的确定可以基于范围变量是否涉及到循环中的非还原数据依赖关系，它们被定义在外部循环中，以及在循环中什么时候定义标量变量。插入的代码可以包括用于在程序运行时执行的指令以确定程序的循环边界，以及发出检查点指令并提交包含程序中的事务区域的指令。事务区域可以包括程序的原始功能和具有非事务负载的自转等待循环，其中，所述旋转等待循环被配置为在当前事务提交之前等待先前线程提交。

4. 发明申请

US20090235237A1 VALUE PREDICTABLE VARIABLE SCOPING FOR SPECULATIVE AUTOMATIC PARALLELIZATION WITH TRANSACTIONAL MEMORY 有权
标题翻译：用于具有可交互存储器的自动并行自动平均值的可预测可变范围
公开(公告)号：US20090235237A1
公开(公告)日：2009-09-17
申请号：US12046365
申请日：2008-03-11
申请人： Yonghong Song , Xiangyun Kong , Spiros Kalogeropulos , Partha P. Tirumalai
发明人： Yonghong Song , Xiangyun Kong , Spiros Kalogeropulos , Partha P. Tirumalai
IPC分类号： G06F9/44
CPC分类号： G06F8/456
摘要： Parallelize a computer program by scoping program variables at compile time and inserting code into the program. Identify as value predictable variables, variables that are: defined only once in a loop of the program; not defined in any inner loop of the loop; and used in the loop. Optionally also: identify a code block in the program that contains a variable assignment, and then traverse a path backwards from the block through a control flow graph of the program. Name in a set all blocks along the path until a loop header block. For each block in the set, determine program blocks that logically succeed the block and are not in the first set. Identify all paths between the block and the determined blocks as failure paths, and insert code into the failure paths. When executed at run time of the program, the inserted code fails the corresponding path.
摘要翻译：通过在编译时对程序变量进行范围并将代码插入程序来并行化计算机程序。识别为值可预测变量，变量是：在程序循环中仅定义一次; 没有在循环的任何内循环中定义; 并在循环中使用。还可以：识别包含变量赋值的程序中的代码块，然后通过程序的控制流程图从块向后移动一个路径。命名一个路径中的所有块，直到循环头块。对于集合中的每个块，确定在块上逻辑成功并且不在第一组中的程序块。将块和确定的块之间的所有路径标识为故障路径，并将代码插入故障路径。当在程序的运行时执行时，插入的代码失败相应的路径。

5. 发明授权

US07458067B1 Method and apparatus for optimizing computer program performance using steered execution 有权
标题翻译：使用转向执行优化计算机程序性能的方法和装置
公开(公告)号：US07458067B1
公开(公告)日：2008-11-25
申请号：US11084656
申请日：2005-03-18
申请人： Partha P. Tirumalai , Spiros Kalogeropulos , Yonghong Song , Kurt J. Goebel
发明人： Partha P. Tirumalai , Spiros Kalogeropulos , Yonghong Song , Kurt J. Goebel
IPC分类号： G06F9/44
CPC分类号： G06F8/443
摘要： One embodiment of the present invention provides a system that facilitates optimizing computer program performance by using steered execution. The system operates by first receiving source code for a computer program, and then compiling a portion of this source code with a first set of optimizations to generate a first compiled portion. The system also compiles the same portion of the source code with a second set of optimizations to generate a second compiled portion. Remaining source code is compiled to generate a third compiled portion. Additionally, a rule is generated for selecting between the first compiled portion and the second compiled portion. Finally, the first compiled portion, the second compiled portion, the third compiled portion, and the rule are combined into an executable output file.
摘要翻译：本发明的一个实施例提供了一种通过使用转向执行来有助于优化计算机程序性能的系统。该系统首先接收计算机程序的源代码，然后用第一组优化来编译该源代码的一部分以生成第一编译部分。该系统还使用第二组优化来编译源代码的相同部分以生成第二编译部分。编译剩余源代码以生成第三编译部分。另外，生成用于在第一编译部分和第二编译部分之间进行选择的规则。最后，将第一编译部分，第二编译部分，第三编译部分和规则组合成可执行输出文件。

6. 发明申请

US20070271565A1 Anticipatory helper thread based code execution 有权
标题翻译：基于预期的助手线程代码执行
公开(公告)号：US20070271565A1
公开(公告)日：2007-11-22
申请号：US11436948
申请日：2006-05-18
申请人： Partha P. Tirumalai , Yonghong Song , Spiros Kalogeropulos
发明人： Partha P. Tirumalai , Yonghong Song , Spiros Kalogeropulos
IPC分类号： G06F9/46
CPC分类号： G06F9/4843 , G06F9/52
摘要： A method and mechanism for using threads in a computing system. A multithreaded computing system is configured to execute a first thread and a second thread. Responsive to the first thread detecting a launch point for a function, the first thread is configured to provide an indication to the second thread that the second thread may begin execution of a given function. The launch point of the function precedes an actual call point of the function in an execution sequence. The second thread is configured to initiate execution of the function in response to the indication. The function includes one or more inputs and the second thread uses anticipated values for each of the one or more inputs. When the first thread reaches a call point for the function, the first thread is configured to use a results of the second thread's execution, in response to determining the anticipated values used by the second thread were correct.
摘要翻译：一种在计算系统中使用线程的方法和机制。多线程计算系统被配置为执行第一线程和第二线程。响应于检测功能的发起点的第一线程，第一线程被配置为向第二线程提供指示第二线程可以开始执行给定功能的指示。该功能的启动点在执行顺序中的函数的实际调用点之前。第二线程被配置为响应于该指示来启动该功能的执行。该功能包括一个或多个输入，第二线程使用一个或多个输入中的每一个的预期值。当第一线程到达功能的调用点时，第一线程被配置为使用第二线程的执行结果，以响应于确定第二线程使用的预期值是正确的。

7. 发明授权

US08612929B2 Compiler implementation of lock/unlock using hardware transactional memory 有权
标题翻译：使用硬件事务内存的编译器实现锁定/解锁
公开(公告)号：US08612929B2
公开(公告)日：2013-12-17
申请号：US12331950
申请日：2008-12-10
申请人： Spiros Kalogeropulos , Yonghong Song , Partha P. Tirumalai
发明人： Spiros Kalogeropulos , Yonghong Song , Partha P. Tirumalai
IPC分类号： G06F9/44 , G06F9/45
CPC分类号： G06F9/52 , G06F8/458 , G06F9/30087 , G06F9/3857
摘要： A system and method for automatic efficient parallelization of code combined with hardware transactional memory support. A software application may contain a transaction synchronization region (TSR) utilizing lock and unlock transaction synchronization function calls for a shared region of memory within a shared memory. The TSR is replaced with two portions of code. The first portion comprises hardware transactional memory primitives in place of lock and unlock function calls. Also, the first portion ensures no other transaction is accessing the shared region without disabling existing hardware transactional memory support. The second portion performs a fail routine, which utilizes lock and unlock transaction synchronization primitives in response to an indication that a failure occurs within said first portion.
摘要翻译：用于自动高效并行化代码并结合硬件事务内存支持的系统和方法。软件应用可以包含利用对共享存储器内的共享存储器区域的锁定和解锁事务同步功能调用的事务同步区域（TSR）。 TSR被替换为两部分代码。第一部分包括代替锁定和解锁功能调用的硬件事务存储器原语。此外，第一部分确保没有其他事务访问共享区域，而不会禁用现有的硬件事务内存支持。第二部分执行故障例程，其响应于在所述第一部分内发生故障的指示，利用锁定和解锁事务同步原语。

8. 发明授权

US08359587B2 Runtime profitability control for speculative automatic parallelization 有权
标题翻译：投机自动并行化的运行时获利控制
公开(公告)号：US08359587B2
公开(公告)日：2013-01-22
申请号：US12113706
申请日：2008-05-01
申请人： Yonghong Song , Spiros Kalogeropulos , Partha P. Tirumalai
发明人： Yonghong Song , Spiros Kalogeropulos , Partha P. Tirumalai
IPC分类号： G06F9/45
CPC分类号： G06F8/456
摘要： A compilation method and mechanism for parallelizing program code. A method for compilation includes analyzing source code and identifying candidate code for parallelization. The method includes parallelizing the candidate code, in response to determining said profitability meets a predetermined criteria; and generating object code corresponding to the source code. The generated object code includes both a non-parallelized version of the candidate code and a parallelized version of the candidate code. During execution of the object code, a dynamic selection between execution of the non-parallelized version of the candidate code and the parallelized version of the candidate code is made. Changing execution from said parallelized version of the candidate code to the non-parallelized version of the candidate code, may be in response to determining a transaction failure count meets a pre-determined threshold. Additionally, changing execution from one version to the other may be in further response to determining an execution time of the parallelized version of the candidate code is greater than an execution time of the non-parallelized version of the candidate code.
摘要翻译：用于并行化程序代码的编译方法和机制。一种编译方法包括分析源代码和识别用于并行化的候选代码。响应于确定所述获利能力满足预定标准，该方法包括并行化候选代码; 并产生与源代码相对应的目标代码。生成的目标代码包括候选代码的非并行化版本和候选代码的并行化版本。在执行对象代码期间，进行候选代码的非并行化版本的执行与候选代码的并行化版本之间的动态选择。将候选代码的所述并行化版本的执行改变为候选代码的非并行化版本可以响应于确定事务故障计数满足预定阈值。此外，将执行从一个版本改变到另一版本可能进一步响应于确定候选代码的并行化版本的执行时间大于候选代码的非并行化版本的执行时间。

9. 发明申请

US20120226892A1 Method and apparatus for generating efficient code for scout thread to prefetch data values for a main thread 审中-公开
标题翻译：用于生成用于侦察线程的有效代码以预取主线程的数据值的方法和装置
公开(公告)号：US20120226892A1
公开(公告)日：2012-09-06
申请号：US11081984
申请日：2005-03-16
申请人： Partha P. Tirumalai , Yonghong Song , Spiros Kalogeropulos
发明人： Partha P. Tirumalai , Yonghong Song , Spiros Kalogeropulos
IPC分类号： G06F9/38 , G06F12/08
CPC分类号： G06F9/3851 , G06F9/383
摘要： One embodiment of the present invention provides a system that generates code for a scout thread to prefetch data values for a main thread. During operation, the system compiles source code for a program to produce executable code for the program. This compilation process involves performing reuse analysis to identify prefetch candidates which are likely to be touched during execution of the program. Additionally, this compilation process produces executable code for the scout thread which contains prefetch instructions to prefetch the identified prefetch candidates for the main thread. In this way, the scout thread can subsequently be executed in parallel with the main thread in advance of where the main thread is executing to prefetch data items for the main thread.
摘要翻译：本发明的一个实施例提供一种系统，其生成侦察线程的代码以预取主线程的数据值。在操作期间，系统编译程序的源代码，以生成程序的可执行代码。该编译过程涉及执行重用分析以识别在执行程序期间可能被触摸的预取候选。此外，该编译过程产生用于侦察线程的可执行代码，其包含预取指令以预取主线程的所识别的预取候选。以这种方式，侦察线程随后可以在主线程正在执行以预取主线程的数据项之前与主线程并行执行。

10. 发明授权

US07950012B2 Facilitating communication and synchronization between main and scout threads 有权
标题翻译：促进主和侦察线程之间的通信和同步
公开(公告)号：US07950012B2
公开(公告)日：2011-05-24
申请号：US11272178
申请日：2005-11-09
申请人： Partha P. Tirumalai , Yonghong Song , Spiros Kalogeropulos
发明人： Partha P. Tirumalai , Yonghong Song , Spiros Kalogeropulos
IPC分类号： G06F9/46 , G06F9/38
CPC分类号： G06F12/0862 , G06F8/4442 , G06F9/485 , G06F9/52 , G06F2212/6028
摘要： One embodiment of the present invention provides a system for communicating and performing synchronization operations between a main thread and a helper-thread. The system starts by executing a program in a main thread. Upon encountering a loop which has associated helper-thread code, the system commences the execution of the code by the helper-thread separately and in parallel with the main thread. While executing the code by the helper-thread, the system periodically checks the progress of the main thread and deactivates the helper-thread if the code being executed by the helper-thread is no longer performing useful work. Hence, the helper-thread is executes in advance of where the main thread is executing to prefetch data items for the main thread without unnecessarily consuming processor resources or hampering the execution of the main thread.
摘要翻译：本发明的一个实施例提供一种用于在主线程和辅助线程之间进行通信和执行同步操作的系统。系统通过在主线程中执行程序来启动。在遇到具有相关联的助手线程代码的循环时，系统通过辅助线程分别开始与主线程并行执行代码。在由辅助线程执行代码的同时，如果由辅助线程执行的代码不再执行有用的工作，则系统将定期检查主线程的进度并停用辅助线程。因此，辅助线程在主线程正在执行的地方执行以预取主线程的数据项，而不必耗费处理器资源或妨碍主线程的执行。

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