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1. 发明授权

US08587026B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08587026B2
公开(公告)日：2013-11-19
申请号：US13313979
申请日：2011-12-07
申请人： Yonggen He , Huojin Tu , Jing Lin
发明人： Yonggen He , Huojin Tu , Jing Lin
IPC分类号： H01L21/02
CPC分类号： H01L29/161 , H01L21/02381 , H01L21/0243 , H01L21/0245 , H01L21/0251 , H01L21/02532 , H01L21/02579 , H01L21/0262 , H01L29/66636 , H01L29/7848
摘要： This invention relates to a semiconductor device and a manufacturing method therefor for reducing stacking faults caused by high content of Ge in an embedded SiGe structure. The semiconductor device comprises a Si substrate with a recess formed therein. A SiGe seed layer is formed on sidewalls of the recess, and a first SiGe layer having a Ge content gradually increased from bottom to top is formed on the recess bottom. A second SiGe layer having a constant content of Ge is formed on the first SiGe layer. The thickness of the first SiGe layer is less than the depth of the recess. The Ge content in the SiGe seed layer is less than the Ge content in the second SiGe layer, and the Ge content at the upper surface of the first SiGe layer is less than or equal to the Ge content in the second SiGe layer.
摘要翻译：本发明涉及一种半导体器件及其制造方法，用于减少嵌入式SiGe结构中Ge含量高的堆垛层错。半导体器件包括其中形成有凹部的Si衬底。在凹槽的侧壁上形成SiGe种子层，并且在凹部底部形成具有从底部到顶部逐渐增加的Ge含量的第一SiGe层。在第一SiGe层上形成具有恒定Ge含量的第二SiGe层。第一SiGe层的厚度小于凹槽的深度。 SiGe种子层中的Ge含量小于第二SiGe层中的Ge含量，并且第一SiGe层的上表面处的Ge含量小于或等于第二SiGe层中的Ge含量。

2. 发明申请

US20130037856A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130037856A1
公开(公告)日：2013-02-14
申请号：US13313979
申请日：2011-12-07
申请人： Yonggen He , Huojin Tu , Jing Lin
发明人： Yonggen He , Huojin Tu , Jing Lin
IPC分类号： H01L29/78 , H01L21/20
CPC分类号： H01L29/161 , H01L21/02381 , H01L21/0243 , H01L21/0245 , H01L21/0251 , H01L21/02532 , H01L21/02579 , H01L21/0262 , H01L29/66636 , H01L29/7848
摘要： This invention relates to a semiconductor device and a manufacturing method therefor for reducing stacking faults caused by high content of Ge in an embedded SiGe structure. The semiconductor device comprises a Si substrate with a recess formed therein. A SiGe seed layer is formed on sidewalls of the recess, and a first SiGe layer having a Ge content gradually increased from bottom to top is formed on the recess bottom. A second SiGe layer having a constant content of Ge is formed on the first SiGe layer. The thickness of the first SiGe layer is less than the depth of the recess. The Ge content in the SiGe seed layer is less than the Ge content in the second SiGe layer, and the Ge content at the upper surface of the first SiGe layer is less than or equal to the Ge content in the second SiGe layer.
摘要翻译：本发明涉及一种半导体器件及其制造方法，用于减少嵌入式SiGe结构中Ge含量高的堆垛层错。半导体器件包括其中形成有凹部的Si衬底。在凹槽的侧壁上形成SiGe种子层，并且在凹部底部形成具有从底部到顶部逐渐增加的Ge含量的第一SiGe层。在第一SiGe层上形成具有恒定Ge含量的第二SiGe层。第一SiGe层的厚度小于凹槽的深度。 SiGe种子层中的Ge含量小于第二SiGe层中的Ge含量，并且第一SiGe层的上表面处的Ge含量小于或等于第二SiGe层中的Ge含量。

3. 发明授权

US08951852B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08951852B2
公开(公告)日：2015-02-10
申请号：US13243563
申请日：2011-09-23
申请人： Yonggen He , Huojin Tu
发明人： Yonggen He , Huojin Tu
IPC分类号： H01L21/336 , H01L29/66 , H01L29/78 , H01L29/165
CPC分类号： H01L29/66545 , H01L29/165 , H01L29/66628 , H01L29/7847 , H01L29/7848
摘要： The disclosure involves a semiconductor device and a manufacturing method thereof. First, a dielectric layer and a stack comprising a Si layer and at least one SiGe layer located on the Si layer are formed in sequence on a substrate. Then the stack and the dielectric layer are patterned to form a dummy gate and a gate dielectric layer, respectively. Next, sidewall spacers are formed on opposite sides of the dummy gate, and source and drain regions with embedded SiGe are formed. Then, the dummy gate is removed to form an opening, in which a gate material such as metal is filled. In RMG techniques, by adopting the stack consisting of Si and SiGe layers as a dummy gate, the method can further increase the compressive stress in the channel of a MOS device and thus improve carrier mobility as compared to traditional polysilicon dummy gate process.
摘要翻译：本发明涉及一种半导体器件及其制造方法。首先，在衬底上依次形成介电层和包括Si层和位于Si层上的至少一个SiGe层的叠层。然后对叠层和电介质层进行图案化以分别形成虚拟栅极和栅极电介质层。接下来，在虚拟栅极的相对侧上形成侧壁间隔物，并且形成具有嵌入的SiGe的源极和漏极区域。然后，去除虚拟栅极以形成开口，其中填充诸如金属的栅极材料。在RMG技术中，通过采用由Si和SiGe层构成的叠层作为虚拟栅极，与传统的多晶硅虚拟栅极工艺相比，该方法可以进一步提高MOS器件沟道中的压应力，从而提高载流子迁移率。

4. 发明申请

US20130017656A1 METHOD OF FABRICATING A SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20130017656A1
公开(公告)日：2013-01-17
申请号：US13289983
申请日：2011-11-04
申请人： Qingsong Wei , Wei Lu , Wuping Liu , Yonggen He
发明人： Qingsong Wei , Wei Lu , Wuping Liu , Yonggen He
IPC分类号： H01L21/336 , H01L21/28
CPC分类号： H01L21/30608 , H01L21/26533 , H01L21/3083 , H01L29/165 , H01L29/66636 , H01L29/7848
摘要： A method of fabricating semiconductor device is provided. First, a recess having a substantially rectangular cross section is formed in a substrate. Then, oxide layers are formed on sidewalls and bottom of the recess by oxygen ion implantation process, wherein oxide layer on sidewalls of recess is thinner than oxide layer on bottom of recess. Thereafter, oxide layer on sidewalls of recess is completely removed, and only a portion of oxide layer on bottom of recess remains. Then, sidewalls of recess are shaped into Σ form by orientation selective wet etching using oxide layer remained on bottom of recess as a stop layer. Finally, oxide layer on bottom of recess is removed. By forming oxide layer on bottom of recess and using it as stop layer in subsequent orientation selective wet etching, the disclosed method can prevent a Σ-shaped recess with a cuspate bottom.
摘要翻译：提供一种制造半导体器件的方法。首先，在基板上形成具有大致矩形截面的凹部。然后，通过氧离子注入工艺在凹槽的侧壁和底部形成氧化物层，其中凹陷侧壁上的氧化物层比凹部底部的氧化物层薄。此后，凹槽侧壁上的氧化物层被完全去除，并且凹部底部仅有一部分氧化物层残留。然后，凹槽的侧壁成形为＆Sgr; 通过使用氧化物层的取向选择性湿法蚀刻形成残留在凹陷的底部作为停止层的形式。最后，去除凹槽底部的氧化物层。通过在凹部的底部形成氧化物层并将其用作随后的取向选择性湿蚀刻中的停止层，所公开的方法可以防止具有尖端底部的“形”凹槽。

5. 发明授权

US08513075B2 Method for manufacturing a semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US08513075B2
公开(公告)日：2013-08-20
申请号：US13306969
申请日：2011-11-29
申请人： Yonggen He , Jingang Wu , Haibiao Yao
发明人： Yonggen He , Jingang Wu , Haibiao Yao
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823864
摘要： A manufacturing method for manufacturing a semiconductor device includes depositing a spacer material on a semiconductor substrate, the substrate includes an NMOS region and a PMOS region, each region has a gate formed thereon. The method further includes covering the NMOS region with a first mask, forming a spacer for the PMOS gate by etching the spacer material, forming a recess in the PMOS region by etching, and growing SiGe or SiGe with in-situ-doped B in the recess of the PMOS region to form a PMOS source/drain region. The method further includes performing an anisotropic wet etching on the recess. After growing SiGE or SiGe with in-situ-doped B, the method further includes covering the PMOS region with a second mask and forming a spacer for the NMOS gate by etching the spacer material. The spacer for the PMOS and NMOS gate has a different critical dimension.
摘要翻译：一种用于制造半导体器件的制造方法，包括在半导体衬底上沉积间隔物材料，所述衬底包括NMOS区域和PMOS区域，每个区域都形成有栅极。该方法还包括用第一掩模覆盖NMOS区域，通过蚀刻间隔物材料形成用于PMOS栅极的间隔物，通过蚀刻在PMOS区域中形成凹陷，并在其中生长具有原位掺杂B的SiGe或SiGe PMOS区域的凹部以形成PMOS源极/漏极区域。该方法还包括在凹部上执行各向异性湿蚀刻。在用原位掺杂的B生长SiGE或SiGe之后，该方法还包括用第二掩模覆盖PMOS区，并通过蚀刻间隔物材料形成NMOS栅的间隔物。用于PMOS和NMOS栅极的间隔物具有不同的临界尺寸。

6. 发明申请

US20120264287A1 METHOD FOR FORMING AN INTERCONNECT STRUCTURE 有权
标题翻译：形成互连结构的方法
公开(公告)号：US20120264287A1
公开(公告)日：2012-10-18
申请号：US13208332
申请日：2011-08-11
申请人： MING ZHOU , Yonggen He
发明人： MING ZHOU , Yonggen He
IPC分类号： H01L21/768
CPC分类号： H01L21/76802 , H01L21/76814 , H01L21/76825 , H01L21/76826
摘要： A method for forming an interconnect structure includes providing a semiconductor substrate having a barrier layer, a low dielectric constant (Low K) inter-dielectric layer and a cap dielectric layer sequentially formed thereon; etching the cap dielectric layer and the Low K inter-dielectric layer sequentially until the barrier layer is exposed and a groove is formed; removing the cap dielectric layer until the Low K inter-dielectric layer is exposed; and doping a carbon element into the Low K inter-dielectric layer. The advantages of the method includes a decrease of the dielectric constant of the Low K inter-dielectric layer, thus, reduces the resistive-capacitive (RC) delay of interconnect layers of a semiconductor device and improve its operating speed and performance.
摘要翻译：一种用于形成互连结构的方法包括提供具有阻挡层，低介电常数（Low K）介电层和顺序形成在其上的盖电介质层的半导体衬底; 依次对盖电介质层和低K介电层进行蚀刻，直到阻挡层露出并形成凹槽; 去除盖电介质层直到露出低K介电层; 并将碳元素掺杂到低K介电层中。该方法的优点包括降低低K介电层的介电常数，从而降低半导体器件的互连层的电阻 - 电容（RC）延迟并提高其工作速度和性能。

7. 发明授权

US09449834B2 Method of fabricating semiconductor devices including PMOS devices having embedded SiGe 有权
标题翻译：制造包括具有嵌入SiGe的PMOS器件的半导体器件的方法
公开(公告)号：US09449834B2
公开(公告)日：2016-09-20
申请号：US13289983
申请日：2011-11-04
申请人： Qingsong Wei , Wei Lu , Wuping Liu , Yonggen He
发明人： Qingsong Wei , Wei Lu , Wuping Liu , Yonggen He
IPC分类号： H01L21/3205 , H01L21/306 , H01L21/265 , H01L29/66 , H01L29/78 , H01L29/165 , H01L21/308
CPC分类号： H01L21/30608 , H01L21/26533 , H01L21/3083 , H01L29/165 , H01L29/66636 , H01L29/7848
摘要： A method of fabricating semiconductor device is provided. First, a recess having a substantially rectangular cross section is formed in a substrate. Then, oxide layers are formed on sidewalls and bottom of the recess by oxygen ion implantation process, wherein oxide layer on sidewalls of recess is thinner than oxide layer on bottom of recess. Thereafter, oxide layer on sidewalls of recess is completely removed, and only a portion of oxide layer on bottom of recess remains. Then, sidewalls of recess are shaped into Σ form by orientation selective wet etching using oxide layer remained on bottom of recess as a stop layer. Finally, oxide layer on bottom of recess is removed. By forming oxide layer on bottom of recess and using it as stop layer in subsequent orientation selective wet etching, the disclosed method can prevent a Σ-shaped recess with a cuspate bottom.
摘要翻译：提供一种制造半导体器件的方法。首先，在基板上形成具有大致矩形截面的凹部。然后，通过氧离子注入工艺在凹槽的侧壁和底部形成氧化物层，其中凹陷侧壁上的氧化物层比凹部底部的氧化物层薄。此后，凹槽侧壁上的氧化物层被完全去除，并且凹部底部仅有一部分氧化物层残留。然后，通过使用保留在凹部底部的氧化物层作为停止层的取向选择性湿蚀刻将凹部的侧壁成形为Σ形式。最后，去除凹槽底部的氧化物层。通过在凹部的底部形成氧化物层并将其用作随后的取向选择性湿蚀刻中的停止层，所公开的方法可以防止具有尖端底部的Σ形凹部。

8. 发明授权

US08372722B2 Method for fabricating a semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US08372722B2
公开(公告)日：2013-02-12
申请号：US13290007
申请日：2011-11-04
申请人： Qingsong Wei , Yonggen He , Huanxin Liu , Jialei Liu , Chaowei Li
发明人： Qingsong Wei , Yonggen He , Huanxin Liu , Jialei Liu , Chaowei Li
IPC分类号： H01L21/336
CPC分类号： H01L21/26533 , H01L21/30617 , H01L21/3083 , H01L29/165 , H01L29/66636 , H01L29/7848
摘要： A method of fabricating semiconductor device includes forming a recess having a substantially rectangular section and forming an oxide layer on sidewalls and an oxide layer on a bottom of the recess by anisotropic oxidation, wherein the oxide layer on the sidewalls is thinner than the oxide layer on the bottom of recess. The method further includes completely removing the oxide layer on the sidewalls and partially removing the oxide layer on the bottom of the recess. The method also includes performing an orientation selective wet etching on the recess using a remaining oxide layer of the recess as a stop layer to shape the sidewalls into a Σ shaped section. The method includes removing the remaining oxide layer using an isotropic wet etching.
摘要翻译：一种制造半导体器件的方法包括：形成具有基本矩形部分的凹槽，并通过各向异性氧化在侧壁上形成氧化物层和位于凹陷底部的氧化物层，其中侧壁上的氧化物层比氧化物层薄底部的凹槽。该方法还包括完全去除侧壁上的氧化物层，并部分去除凹部底部的氧化物层。所述方法还包括使用所述凹部的剩余氧化物层作为停止层来在所述凹部上执行取向选择性湿蚀刻，以将所述侧壁成形为“ 形截面。该方法包括使用各向同性湿蚀刻去除剩余的氧化物层。

9. 发明授权

US08354341B2 Method for forming an interconnect structure 有权
标题翻译：形成互连结构的方法
公开(公告)号：US08354341B2
公开(公告)日：2013-01-15
申请号：US13208332
申请日：2011-08-11
申请人： Ming Zhou , Yonggen He
发明人： Ming Zhou , Yonggen He
IPC分类号： H01L21/4763
CPC分类号： H01L21/76802 , H01L21/76814 , H01L21/76825 , H01L21/76826
摘要： A method for forming an interconnect structure includes providing a semiconductor substrate having a barrier layer, a low dielectric constant (Low K) inter-dielectric layer and a cap dielectric layer sequentially formed thereon; etching the cap dielectric layer and the Low K inter-dielectric layer sequentially until the barrier layer is exposed and a groove is formed; removing the cap dielectric layer until the Low K inter-dielectric layer is exposed; and doping a carbon element into the Low K inter-dielectric layer. The advantages of the method includes a decrease of the dielectric constant of the Low K inter-dielectric layer, thus, reduces the resistive-capacitive (RC) delay of interconnect layers of a semiconductor device and improve its operating speed and performance.
摘要翻译：一种用于形成互连结构的方法包括提供具有阻挡层，低介电常数（Low K）介电层和顺序形成在其上的盖电介质层的半导体衬底; 依次对盖电介质层和低K介电层进行蚀刻，直到阻挡层露出并形成凹槽; 去除盖电介质层直到露出低K介电层; 并将碳元素掺杂到低K介电层中。该方法的优点包括降低低K介电层的介电常数，从而降低半导体器件的互连层的电阻 - 电容（RC）延迟并提高其工作速度和性能。

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