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1. 发明授权

US07687357B2 Semiconductor device and method for fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07687357B2
公开(公告)日：2010-03-30
申请号：US11965679
申请日：2007-12-27
申请人： Yong-Soo Kim , Hong-Seon Yang , Seung-Ho Pyi , Tae-Hang Ahn
发明人： Yong-Soo Kim , Hong-Seon Yang , Seung-Ho Pyi , Tae-Hang Ahn
IPC分类号： H01L21/8234 , H01L27/088
CPC分类号： H01L29/0847 , H01L21/18 , H01L29/165 , H01L29/66636 , H01L29/7848
摘要： A method for fabricating a transistor, the method includes forming a gate over a substrate to form a first resultant structure, forming a gate spacer at first and second sidewalls of the gate, etching portions of the substrate proximate to the gate spacer to form a recess in a source/drain region of the substrate, forming a first epitaxial layer including germanium to fill the recess, and performing a high temperature oxidation process to form a second epitaxial layer including germanium over an interfacial layer between the substrate and the first epitaxial layer, the second epitaxial layer having a germanium concentration that is higher than a germanium concentration of the first epitaxial SiGe layer, thereby forming a second resultant structure.
摘要翻译：一种用于制造晶体管的方法，该方法包括在衬底上形成栅极以形成第一结构结构，在栅极的第一和第二侧壁处形成栅极间隔物，蚀刻靠近栅极间隔物的衬底的部分以形成凹陷在衬底的源极/漏极区域中形成包括锗的第一外延层以填充凹槽，并且进行高温氧化工艺以在衬底和第一外延层之间的界面层上形成包括锗的第二外延层，所述第二外延层的锗浓度高于所述第一外延SiGe层的锗浓度，从而形成第二结晶结构。

2. 发明申请

US20090001418A1 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090001418A1
公开(公告)日：2009-01-01
申请号：US11965679
申请日：2007-12-27
申请人： Yong-Soo KIM , Hong-Seon Yang , Seung-Ho Pyi , Tae-Hang Ahn
发明人： Yong-Soo KIM , Hong-Seon Yang , Seung-Ho Pyi , Tae-Hang Ahn
IPC分类号： H01L27/088 , H01L21/8234
CPC分类号： H01L29/0847 , H01L21/18 , H01L29/165 , H01L29/66636 , H01L29/7848
摘要： A method for fabricating a transistor, the method includes forming a gate over a substrate to form a first resultant structure, forming a gate spacer at first and second sidewalls of the gate, etching portions of the substrate proximate to the gate spacer to form a recess in a source/drain region of the substrate, forming a first epitaxial layer including germanium to fill the recess, and performing a high temperature oxidation process to form a second epitaxial layer including germanium over an interfacial layer between the substrate and the first epitaxial layer, the second epitaxial layer having a germanium concentration that is higher than a germanium concentration of the first epitaxial SiGe layer, thereby forming a second resultant structure.
摘要翻译：一种用于制造晶体管的方法，该方法包括在衬底上形成栅极以形成第一结构结构，在栅极的第一和第二侧壁处形成栅极间隔物，蚀刻靠近栅极间隔物的衬底的部分以形成凹陷在衬底的源极/漏极区域中形成包括锗的第一外延层以填充凹槽，并且进行高温氧化工艺以在衬底和第一外延层之间的界面层上形成包括锗的第二外延层，所述第二外延层的锗浓度高于所述第一外延SiGe层的锗浓度，从而形成第二结晶结构。

3. 发明授权

US07968912B2 Semiconductor device and method for fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07968912B2
公开(公告)日：2011-06-28
申请号：US12749176
申请日：2010-03-29
申请人： Yong-Soo Kim , Hong-Seon Yang , Seung-Ho Pyi , Tae-Hang Ahn
发明人： Yong-Soo Kim , Hong-Seon Yang , Seung-Ho Pyi , Tae-Hang Ahn
IPC分类号： H01L29/78 , H01L27/12
CPC分类号： H01L29/0847 , H01L21/18 , H01L29/165 , H01L29/66636 , H01L29/7848
摘要： A semiconductor device includes a substrate, a gate formed over the substrate, a gate spacer provided against first and second sidewalls of the gate, and a source/drain region formed in the substrate proximate to the gate spacer. The source/drain region includes first and second epitaxial layers including Ge, wherein the second epitaxial layer which is formed over an interfacial layer between the first epitaxial layer and the substrate has a higher germanium concentration than that of the first epitaxial layer.
摘要翻译：半导体器件包括衬底，形成在衬底上的栅极，设置在栅极的第一和第二侧壁上的栅极间隔，以及形成在靠近栅极间隔物的衬底中的源/漏区。源极/漏极区包括包括Ge的第一和第二外延层，其中在第一外延层和衬底之间的界面层上形成的第二外延层具有比第一外延层更高的锗浓度。

4. 发明授权

US07838364B2 Semiconductor device with bulb-type recessed channel and method for fabricating the same 有权
标题翻译：具有灯泡型凹槽的半导体器件及其制造方法
公开(公告)号：US07838364B2
公开(公告)日：2010-11-23
申请号：US11862453
申请日：2007-09-27
申请人： Yong-Soo Kim , Hong-Seon Yang , Se-Aug Jang , Seung-Ho Pyi , Kwon Hong , Heung-Jae Cho , Kwan-Yong Lim , Min-Gyu Sung , Seung-Ryong Lee , Tae-Yoon Kim
发明人： Yong-Soo Kim , Hong-Seon Yang , Se-Aug Jang , Seung-Ho Pyi , Kwon Hong , Heung-Jae Cho , Kwan-Yong Lim , Min-Gyu Sung , Seung-Ryong Lee , Tae-Yoon Kim
IPC分类号： H01L21/336
CPC分类号： H01L29/66553 , H01L27/10876 , H01L29/518 , H01L29/66621
摘要： A method for fabricating a semiconductor device includes providing a substrate having a bulb-type recessed region, forming a gate insulating layer over the bulb-type recessed region and the substrate, and forming a gate conductive layer over the gate insulating layer. The gate conductive layer fills the bulb-type recessed region. The gate conductive layer includes two or more conductive layers and a discontinuous interface between the conductive layers.
摘要翻译：一种制造半导体器件的方法，包括提供具有灯泡型凹陷区域的衬底，在灯泡型凹陷区域上形成栅极绝缘层和衬底，并在栅极绝缘层上形成栅极导电层。栅极导电层填充灯泡型凹陷区域。栅极导电层包括两个或多个导电层和导电层之间的不连续界面。

5. 发明申请

US20080079048A1 SEMICONDUCTOR DEVICE WITH BULB-TYPE RECESSED CHANNEL AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：具有BULB类型的通道的半导体器件及其制造方法
公开(公告)号：US20080079048A1
公开(公告)日：2008-04-03
申请号：US11862453
申请日：2007-09-27
申请人： Yong-Soo Kim , Hong-Seon Yang , Se-Aug Jang , Seung-Ho Pyi , Kwon Hong , Heung-Jae Cho , Kwan-Yong Lim , Min-Gyu Sung , Seung-Ryong Lee , Tae-Yoon Kim
发明人： Yong-Soo Kim , Hong-Seon Yang , Se-Aug Jang , Seung-Ho Pyi , Kwon Hong , Heung-Jae Cho , Kwan-Yong Lim , Min-Gyu Sung , Seung-Ryong Lee , Tae-Yoon Kim
IPC分类号： H01L27/108 , H01L21/3205
CPC分类号： H01L29/66553 , H01L27/10876 , H01L29/518 , H01L29/66621
摘要： A method for fabricating a semiconductor device includes providing a substrate having a bulb-type recessed region, forming a gate insulating layer over the bulb-type recessed region and the substrate, and forming a gate conductive layer over the gate insulating layer. The gate conductive layer fills the bulb-type recessed region. The gate conductive layer includes two or more conductive layers and a discontinuous interface between the conductive layers.
摘要翻译：一种制造半导体器件的方法，包括提供具有灯泡型凹陷区域的衬底，在灯泡型凹陷区域上形成栅极绝缘层和衬底，并在栅极绝缘层上形成栅极导电层。栅极导电层填充灯泡型凹陷区域。栅极导电层包括两个或多个导电层和导电层之间的不连续界面。

6. 发明授权

US08928063B2 Non-volatile memory device and method for fabricating the same 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US08928063B2
公开(公告)日：2015-01-06
申请号：US13618182
申请日：2012-09-14
申请人： Min-Soo Kim , Dong-Sun Sheen , Seung-Ho Pyi , Sung-Jin Whang
发明人： Min-Soo Kim , Dong-Sun Sheen , Seung-Ho Pyi , Sung-Jin Whang
IPC分类号： H01L29/792 , H01L21/20
CPC分类号： H01L21/28282 , H01L27/11582 , H01L29/66666 , H01L29/66833 , H01L29/792
摘要： A non-volatile memory device includes a channel layer vertically extending from a substrate, a plurality of inter-layer dielectric layers and a plurality of gate electrodes that are alternately stacked along the channel layer, and an air gap interposed between the channel layer and each of the plurality of gate electrodes. The non-volatile memory device may improve erase operation characteristics by suppressing back tunneling of electrons by substituting a charge blocking layer interposed between a gate electrode and a charge storage layer with an air gap, and a method for fabricating the non-volatile memory device.
摘要翻译：非易失性存储器件包括从衬底垂直延伸的沟道层，沿着沟道层交替层叠的多个层间电介质层和多个栅极电极，以及插入在沟道层和每个沟道层之间的气隙的多个栅电极。非易失性存储器件可以通过用插入位于栅电极和具有气隙的电荷存储层之间的电荷阻挡层来抑制电子的反向隧道而提高擦除操作特性，以及制造非易失性存储器件的方法。

7. 发明申请

US20090278225A1 SEMICONDUCTOR DEVICE AND METHOD FOR ISOLATING THE SAME 有权
标题翻译：半导体器件及其分离方法
公开(公告)号：US20090278225A1
公开(公告)日：2009-11-12
申请号：US12504427
申请日：2009-07-16
申请人： Seung-Ho Pyi
发明人： Seung-Ho Pyi
IPC分类号： H01L29/06
CPC分类号： H01L21/76232 , H01L21/764 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to a semiconductor device and a method for isolating the same. The semiconductor device includes: a silicon substrate provided with a trench including at least one silicon pillar at a bottom portion of the trench, wherein the silicon pillar become sidewalls of micro trenches; and a device isolation layer selectively and partially filled into the plurality of micro trenches.
摘要翻译：本发明涉及半导体器件及其分离方法。半导体器件包括：硅衬底，其设置有在沟槽的底部具有至少一个硅柱的沟槽，其中硅柱变成微沟槽的侧壁; 以及选择性地和部分地填充到多个微沟槽中的器件隔离层。

8. 发明申请

US20070138641A1 Semiconductor device and method for fabricating the same 审中-公开
公开(公告)号：US20070138641A1
公开(公告)日：2007-06-21
申请号：US11705511
申请日：2007-02-13
申请人： Seung-Ho Pyi
发明人： Seung-Ho Pyi
IPC分类号： H01L23/52 , H01L23/48 , H01L29/40
CPC分类号： H01L21/76838 , H01L21/76895 , H01L27/10885 , H01L27/10894
摘要： The present invention relates to a semiconductor device with an improved contact margin between an interconnection line and a bit line and a method for fabricating the same. The semiconductor device includes: a bit line structure formed on a substrate and having a number of bit lines and a pad; a first inter-layer insulation layer formed on the bit line structure and the substrate and having a first opening exposing the pad; a conductive layer formed on the first inter-layer insulation layer and patterned to be a middle pad filled into the first opening and a plate electrode of a capacitor; a second inter-layer insulation layer formed on the first inter-layer insulation layer and the patterned conductive layer and having a second opening exposing the middle pad; and a metal layer filled into the second opening to form an interconnection line contacted to the pad.

9. 发明申请

US20060014372A1 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060014372A1
公开(公告)日：2006-01-19
申请号：US11023348
申请日：2004-12-29
申请人： Seung-Ho Pyi
发明人： Seung-Ho Pyi
IPC分类号： H01L21/00
CPC分类号： H01L21/76838 , H01L21/76895 , H01L27/10885 , H01L27/10894
摘要： The present invention relates to a semiconductor device with an improved contact margin between an interconnection line and a bit line and a method for fabricating the same. The semiconductor device includes: a bit line structure formed on a substrate and having a number of bit lines and a pad; a first inter-layer insulation layer formed on the bit line structure and the substrate and having a first opening exposing the pad; a conductive layer formed on the first inter-layer insulation layer and patterned to be a middle pad filled into the first opening and a plate electrode of a capacitor; a second inter-layer insulation layer formed on the first inter-layer insulation layer and the patterned conductive layer and having a second opening exposing the middle pad; and a metal layer filled into the second opening to form an interconnection line contacted to the pad.
摘要翻译：本发明涉及一种在互连线和位线之间具有改善的接触裕度的半导体器件及其制造方法。半导体器件包括：形成在衬底上并具有多个位线和衬垫的位线结构; 形成在所述位线结构和所述基板上的第一层间绝缘层，并且具有暴露所述焊盘的第一开口; 形成在所述第一层间绝缘层上且被图案化为填充到所述第一开口中的中间焊盘和电容器的板电极的导电层; 形成在所述第一层间绝缘层和所述图案化导电层上并具有暴露所述中间焊盘的第二开口的第二层间绝缘层; 以及填充到所述第二开口中的金属层，以形成与所述垫接触的互连线。

10. 发明授权

US07189597B2 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07189597B2
公开(公告)日：2007-03-13
申请号：US11023348
申请日：2004-12-29
申请人： Seung-Ho Pyi
发明人： Seung-Ho Pyi
IPC分类号： H01L21/00
CPC分类号： H01L21/76838 , H01L21/76895 , H01L27/10885 , H01L27/10894
摘要： The present invention relates to a semiconductor device with an improved contact margin between an interconnection line and a bit line and a method for fabricating the same. The semiconductor device includes: a bit line structure formed on a substrate and having a number of bit lines and a pad; a first inter-layer insulation layer formed on the bit line structure and the substrate and having a first opening exposing the pad; a conductive layer formed on the first inter-layer insulation layer and patterned to be a middle pad filled into the first opening and a plate electrode of a capacitor; a second inter-layer insulation layer formed on the first inter-layer insulation layer and the patterned conductive layer and having a second opening exposing the middle pad; and a metal layer filled into the second opening to form an interconnection line contacted to the pad.
摘要翻译：本发明涉及一种在互连线和位线之间具有改善的接触裕度的半导体器件及其制造方法。半导体器件包括：形成在衬底上并具有多个位线和衬垫的位线结构; 形成在所述位线结构和所述基板上的第一层间绝缘层，并且具有暴露所述焊盘的第一开口; 形成在所述第一层间绝缘层上且被图案化为填充到所述第一开口中的中间焊盘和电容器的板电极的导电层; 形成在所述第一层间绝缘层和所述图案化导电层上并具有暴露所述中间焊盘的第二开口的第二层间绝缘层; 以及填充到所述第二开口中的金属层，以形成与所述垫接触的互连线。

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