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1. 发明授权

US08692824B2 LCD driving apparatus and method 有权
标题翻译： LCD驱动装置及方法
公开(公告)号：US08692824B2
公开(公告)日：2014-04-08
申请号：US12261559
申请日：2008-10-30
申请人： Yong-Nien Rao , Yu-Lung Lo , Chih-Yu Lee
发明人： Yong-Nien Rao , Yu-Lung Lo , Chih-Yu Lee
IPC分类号： G06F3/038 , G09G5/00 , G09G3/36
CPC分类号： G09G3/3696 , G09G2320/0233
摘要： The invention discloses a driving apparatus for driving an LCD. The driving apparatus comprises a voltage control unit, an operating unit, a resistance unit, and a voltage selection unit. The operating unit comprises two sets of buffers formed by a plurality of operational amplifiers in negative feedback circuit. The two sets of buffers selectively receive positive polarity voltages and negative polarity voltages respectively. The voltage selection unit is provided with the positive polarity voltages and negative polarity voltages through the operating unit and the resistance unit. The voltage selection unit selectively provides the pixels of the LCD with the positive polarity voltage and the negative polarity voltage. Accordingly, each of the pixels is provided either with the positive polarity voltages or the negative polarity voltages by one of the two sets of buffers.
摘要翻译：本发明公开了一种用于驱动LCD的驱动装置。驱动装置包括电压控制单元，操作单元，电阻单元和电压选择单元。操作单元包括由负反馈电路中的多个运算放大器形成的两组缓冲器。两组缓冲器分别选择性地接收正极性电压和负极性电压。电压选择单元通过操作单元和电阻单元提供正极性电压和负极性电压。电压选择单元选择性地为LCD的像素提供正极性电压和负极性电压。因此，通过两组缓冲器之一，每个像素都由正极性电压或负极性电压提供。

2. 发明申请

US20090141016A1 LCD DRIVING APPARATUS AND METHOD 有权
标题翻译： LCD驱动装置和方法
公开(公告)号：US20090141016A1
公开(公告)日：2009-06-04
申请号：US12261559
申请日：2008-10-30
申请人： Yong-Nien Rao , Yu-Lung Lo , Chih-Yu Lee
发明人： Yong-Nien Rao , Yu-Lung Lo , Chih-Yu Lee
IPC分类号： G06F3/038
CPC分类号： G09G3/3696 , G09G2320/0233
摘要： The invention discloses a driving apparatus for driving an LCD. The driving apparatus comprises a voltage control unit, an operating unit, a resistance unit, and a voltage selection unit. The operating unit comprises two sets of buffers formed by a plurality of operational amplifiers in negative feedback circuit. The two sets of buffers selectively receive positive polarity voltages and negative polarity voltages respectively. The voltage selection unit is provided with the positive polarity voltages and negative polarity voltages through the operating unit and the resistance unit. The voltage selection unit selectively provides the pixels of the LCD with the positive polarity voltage and the negative polarity voltage. Accordingly, each of the pixels is provided either with the positive polarity voltages or the negative polarity voltages by one of the two sets of buffers.
摘要翻译：本发明公开了一种用于驱动LCD的驱动装置。驱动装置包括电压控制单元，操作单元，电阻单元和电压选择单元。操作单元包括由负反馈电路中的多个运算放大器形成的两组缓冲器。两组缓冲器分别选择性地接收正极性电压和负极性电压。电压选择单元通过操作单元和电阻单元提供正极性电压和负极性电压。电压选择单元选择性地为LCD的像素提供正极性电压和负极性电压。因此，通过两组缓冲器之一，每个像素都由正极性电压或负极性电压提供。

3. 发明授权

US07656203B2 Receiving circuit and method thereof 有权
标题翻译：接收电路及其方法
公开(公告)号：US07656203B2
公开(公告)日：2010-02-02
申请号：US12073196
申请日：2008-03-03
申请人： Chih-Yu Lee , Yong-Nien Rao , Ko-Yang Tso , Hui-Wen Miao , Chin-Chieh Chao
发明人： Chih-Yu Lee , Yong-Nien Rao , Ko-Yang Tso , Hui-Wen Miao , Chin-Chieh Chao
IPC分类号： H03B1/00
CPC分类号： H04L25/0292 , H04L25/0272
摘要： A receiving circuit is provided for receiving a data signal and a clock signal, which are RSDS signals, and outputting an output data signal to a data driver. The receiving circuit includes a data comparator, a data intermediate circuit, a clock comparator, a clock intermediate, and a flip-flop. The data comparator, driven with a data bias current, receives the data signal, and outputs a compared data signal. The clock comparator, driven with a clock bias current, receives the clock signal, and outputs a compared clock signal. The flip-flop receives the compared data signal via the data intermediate circuit and the compared clock signal via the clock intermediate circuit. The phase difference between the compared data signal and the compared clock signal is improved by adjusting the data and the clock bias currents.
摘要翻译：提供接收电路，用于接收作为RSDS信号的数据信号和时钟信号，并将输出数据信号输出到数据驱动器。接收电路包括数据比较器，数据中间电路，时钟比较器，时钟中间和触发器。由数据偏置电流驱动的数据比较器接收数据信号，并输出比较的数据信号。由时钟偏置电流驱动的时钟比较器接收时钟信号，并输出比较的时钟信号。触发器经由时钟中间电路经由数据中间电路和经比较的时钟信号接收比较的数据信号。通过调整数据和时钟偏置电流，可以提高比较数据信号与比较时钟信号之间的相位差。

4. 发明申请

US20080253482A1 Receiving circuit and method thereof 有权
标题翻译：接收电路及其方法
公开(公告)号：US20080253482A1
公开(公告)日：2008-10-16
申请号：US12073196
申请日：2008-03-03
申请人： Chih-Yu Lee , Yong-Nien Rao , Ko-Yang Tso , Hui-Wen Miao , Chin-Chieh Chao
发明人： Chih-Yu Lee , Yong-Nien Rao , Ko-Yang Tso , Hui-Wen Miao , Chin-Chieh Chao
IPC分类号： H03K9/00 , H04L27/00
CPC分类号： H04L25/0292 , H04L25/0272
摘要： A receiving circuit is provided for receiving a data signal and a clock signal, which are RSDS signals, and outputting an output data signal to a data driver. The receiving circuit includes a data comparator, a data intermediate circuit, a clock comparator, a clock intermediate, and a flip-flop. The data comparator, driven with a data bias current, receives the data signal, and outputs a compared data signal. The clock comparator, driven with a clock bias current, receives the clock signal, and outputs a compared clock signal. The flip-flop receives the compared data signal via the data intermediate circuit and the compared clock signal via the clock intermediate circuit. The phase difference between the compared data signal and the compared clock signal is improved by adjusting the data and the clock bias currents.
摘要翻译：提供接收电路，用于接收作为RSDS信号的数据信号和时钟信号，并将输出数据信号输出到数据驱动器。接收电路包括数据比较器，数据中间电路，时钟比较器，时钟中间和触发器。由数据偏置电流驱动的数据比较器接收数据信号，并输出比较的数据信号。由时钟偏置电流驱动的时钟比较器接收时钟信号，并输出比较的时钟信号。触发器经由时钟中间电路经由数据中间电路和经比较的时钟信号接收比较的数据信号。通过调整数据和时钟偏置电流，改善了比较数据信号与比较时钟信号之间的相位差。

5. 发明授权

US06818515B1 Method for fabricating semiconductor device with loop line pattern structure 有权
标题翻译：制造具有环线图形结构的半导体器件的方法
公开(公告)号：US06818515B1
公开(公告)日：2004-11-16
申请号：US10600466
申请日：2003-06-23
申请人： Brian S. Lee , Chih-Yu Lee
发明人： Brian S. Lee , Chih-Yu Lee
IPC分类号： H01L21336
CPC分类号： H01L21/32139 , G03F1/30 , H01L27/10861 , H01L27/10891
摘要： An alternating phase shift mask with dark loops thereon, a memory array fabricated with the alternating phase shift mask, and a method of fabricating the memory. The dark loops in the mask always separate first regions with 180° phase difference from second regions with 0° phase difference to define active areas or gate-lines in a DRAM chip.
摘要翻译：具有暗环的交替相移掩模，用交替相移掩模制造的存储器阵列，以及制造存储器的方法。掩模中的暗环总是将具有180°相位差的第一区域与具有0°相位差的第二区域分开，以限定DRAM芯片中的有源区或栅极线。

6. 发明授权

US07402364B2 Semiconductor device with loop line pattern structure, method and alternating phase shift mask for fabricating the same 有权
标题翻译：具有环线图案结构的半导体器件，用于制造其的交替相移掩模
公开(公告)号：US07402364B2
公开(公告)日：2008-07-22
申请号：US10957678
申请日：2004-10-05
申请人： Brian S. Lee , Chih-Yu Lee
发明人： Brian S. Lee , Chih-Yu Lee
IPC分类号： G03F1/00
CPC分类号： H01L21/32139 , G03F1/30 , H01L27/10861 , H01L27/10891
摘要： An alternating phase shift mask with dark loops thereon, a memory array fabricated with the alternating phase shift mask, and a method of fabricating the memory. The dark loops in the mask always separate first regions with 180° phase difference from second regions with 0° phase difference to define active areas or gate-lines in a DRAM chip. By using the alternating phase shift mask to pattern gate-lines or active areas in a DRAM array, no unwanted image is created in the DRAM array and only one exposure is needed to achieve high resolution requirement.
摘要翻译：具有暗环的交替相移掩模，用交替相移掩模制造的存储器阵列，以及制造存储器的方法。掩模中的暗环总是将具有180°相位差的第一区域与具有0°相位差的第二区域分开，以限定DRAM芯片中的有源区域或栅极线。通过使用交替相移掩模来对DRAM阵列中的栅极线或有源区进行图案化，在DRAM阵列中不产生不需要的图像，并且仅需要一次曝光来实现高分辨率要求。

7. 发明申请

US20050079427A1 Semiconductor device with loop line pattern structure, method and alternating phase shift mask for fabricating the same 有权
公开(公告)号：US20050079427A1
公开(公告)日：2005-04-14
申请号：US10957678
申请日：2004-10-05
申请人： Brian Lee , Chih-Yu Lee
发明人： Brian Lee , Chih-Yu Lee
IPC分类号： G03C5/00 , G03F1/00 , G03F9/00 , H01L21/3213 , H01L21/336 , H01L21/8242 , H01L27/108
CPC分类号： H01L21/32139 , G03F1/30 , H01L27/10861 , H01L27/10891
摘要： An alternating phase shift mask with dark loops thereon, a memory array fabricated with the alternating phase shift mask, and a method of fabricating the memory. The dark loops in the mask always separate first regions with 180° phase difference from second regions with 0° phase difference to define active areas or gate-lines in a DRAM chip. By using the alternating phase shift mask to pattern gate-lines or active areas in a DRAM array, no unwanted image is created in the DRAM array and only one exposure is needed to achieve high resolution requirement.

8. 发明申请

US20050057998A1 Semiconductor device with loop line pattern structure, method and alternating phase shift mask for fabricating the same 有权
标题翻译：具有环线图案结构的半导体器件，用于制造其的交替相移掩模
公开(公告)号：US20050057998A1
公开(公告)日：2005-03-17
申请号：US10957688
申请日：2004-10-05
申请人： Brian Lee , Chih-Yu Lee
发明人： Brian Lee , Chih-Yu Lee
IPC分类号： G03C5/00 , G03F1/00 , G03F9/00 , H01L21/3213 , H01L21/336 , H01L21/8242 , H01L27/108
CPC分类号： H01L21/32139 , G03F1/30 , H01L27/10861 , H01L27/10891
摘要： An alternating phase shift mask with dark loops thereon, a memory array fabricated with the alternating phase shift mask, and a method of fabricating the memory. The dark loops in the mask always separate first regions with 180° phase difference from second regions with 0° phase difference to define active areas or gate-lines in a DRAM chip. By using the alternating phase shift mask to pattern gate-lines or active areas in a DRAM array, no unwanted image is created in the DRAM array and only one exposure is needed to achieve high resolution requirement.
摘要翻译：具有暗环的交替相移掩模，用交替相移掩模制造的存储器阵列，以及制造存储器的方法。掩模中的暗环总是将具有180°相位差的第一区域与具有0°相位差的第二区域分开，以限定DRAM芯片中的有源区域或栅极线。通过使用交替相移掩模来对DRAM阵列中的栅极线或有源区进行图案化，在DRAM阵列中不产生不需要的图像，并且仅需要一次曝光来实现高分辨率要求。

9. 发明授权

US07087947B2 Semiconductor device with loop line pattern structure, method and alternating phase shift mask for fabricating the same 有权
标题翻译：具有环线图案结构的半导体器件，用于制造其的交替相移掩模
公开(公告)号：US07087947B2
公开(公告)日：2006-08-08
申请号：US10957688
申请日：2004-10-05
申请人： Brian S. Lee , Chih-Yu Lee
发明人： Brian S. Lee , Chih-Yu Lee
IPC分类号： H01L27/108
CPC分类号： H01L21/32139 , G03F1/30 , H01L27/10861 , H01L27/10891
摘要： An alternating phase shift mask with dark loops thereon, a memory array fabricated with the alternating phase shift mask, and a method of fabricating the memory. The dark loops in the mask always separate first regions with 180° phase difference from second regions with 0° phase difference to define active areas or gate-lines in a DRAM chip. By using the alternating phase shift mask to pattern gate-lines or active areas in a DRAM array, no unwanted image is created in the DRAM array and only one exposure is needed to achieve high resolution requirement.
摘要翻译：具有暗环的交替相移掩模，用交替相移掩模制造的存储器阵列，以及制造存储器的方法。掩模中的暗环总是将具有180°相位差的第一区域与具有0°相位差的第二区域分开，以限定DRAM芯片中的有源区域或栅极线。通过使用交替相移掩模来对DRAM阵列中的栅极线或有源区进行图案化，在DRAM阵列中不产生不需要的图像，并且仅需要一次曝光来实现高分辨率要求。

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