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1. 发明授权

US07505887B1 Building a simulation of design block using a bus functional model and an HDL testbench 有权
标题翻译：使用总线功能模型和HDL测试平台构建设计模块
公开(公告)号：US07505887B1
公开(公告)日：2009-03-17
申请号：US11344475
申请日：2006-01-31
申请人： John A. Canaris , Jorge Ernesto Carrillo , Lester S. Sanders , Yong Zhu
发明人： John A. Canaris , Jorge Ernesto Carrillo , Lester S. Sanders , Yong Zhu
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： Methods and systems for building a simulation for verifying a design block, including efficient coordination of the control and validation of the operation of a first and second bus of the design block, with the first bus being an interface bus of a processor. An interface description is determined for a bus functional model of the interface bus of the processor. The interface description includes a synchronization bus for coordinating the bus functional model and a hardware description language (HDL) testbench. A hardware specification is generated that couples the first bus of the design block with the interface description, and couples the HDL testbench with the second bus of the design block and with the synchronization bus of the interface description. The simulation for verifying the design block is automatically generated from the bus functional model and the hardware specification.
摘要翻译：用于构建用于验证设计块的模拟的方法和系统，包括对设计块的第一和第二总线的操作的控制和验证的有效协调，第一总线是处理器的接口总线。为处理器的接口总线的总线功能模型确定接口描述。接口描述包括用于协调总线功能模型和硬件描述语言（HDL）测试平台的同步总线。生成将设计块的第一个总线与接口描述相连接的硬件规范，并将HDL测试台与设计块的第二个总线以及接口描述的同步总线相连接。用于验证设计块的仿真是从总线功能模型和硬件规范自动生成的。

2. 发明授权

US07386827B1 Building a simulation environment for a design block 有权
标题翻译：为设计块构建仿真环境
公开(公告)号：US07386827B1
公开(公告)日：2008-06-10
申请号：US11449279
申请日：2006-06-08
申请人： Yong Zhu , Jorge Ernesto Carrillo
发明人： Yong Zhu , Jorge Ernesto Carrillo
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A method is provided for building a simulation environment. A first functional model is produced that emulates the interaction of a processor with a first interface of a bus for the processor as controlled by a first script. A second functional model is produced that is controllable to emulate multiple interfaces. The second functional model is controlled to emulate a second interface of an input/output peripheral by a second script. A third functional model is produced that emulates a memory subsystem. A simulation environment is automatically generated that simulates the design block for a programmable logic device. The simulation environment couples the bus to the design block and the first and third functional models, couples the second interface to the design block and the second functional model, and couples the first and second functional models via a synchronization bus used for synchronizing between transactions of the first and second scripts.
摘要翻译：提供了一种构建仿真环境的方法。产生了第一功能模型，其模拟处理器与由第一脚本控制的处理器的总线的第一接口的交互。产生可以模拟多个接口的第二个功能模型。控制第二功能模型以通过第二脚本模拟输入/输出外围设备的第二接口。产生了模拟存储器子系统的第三个功能模型。自动生成模拟环境，模拟可编程逻辑器件的设计块。模拟环境将总线耦合到设计块和第一和第三功能模型，将第二接口耦合到设计块和第二功能模型，并且经由用于在交易之间的同步的同步总线耦合第一和第二功能模型第一和第二个脚本。

3. 发明授权

US07490227B1 Method and system to recreate instruction and data traces in an embedded processor 有权
标题翻译：在嵌入式处理器中重新创建指令和数据跟踪的方法和系统
公开(公告)号：US07490227B1
公开(公告)日：2009-02-10
申请号：US10930437
申请日：2004-08-31
申请人： Goran Bilski , Jorge Ernesto Carrillo , Usha Prabhu , Navaneethan Sundaramoorthy
发明人： Goran Bilski , Jorge Ernesto Carrillo , Usha Prabhu , Navaneethan Sundaramoorthy
IPC分类号： G06F11/25
CPC分类号： G06F11/3476
摘要： A method of recreating instructions and data traces in a processor can include the step of fetching an instruction from an executable program in an order corresponding to sequential program counter (PC) values, obtaining a destination register from the fetched instruction and updating the destination register in a data structure with a value from a collected destination register corresponding to the PC value. The steps above can be repeated until all desired PC values and destination values are obtained.
摘要翻译：在处理器中重建指令和数据迹线的方法可以包括以与顺序程序计数器（PC）值相对应的顺序从可执行程序获取指令的步骤，从获取的指令获取目的地寄存器并且更新目的地寄存器具有来自与PC值相对应的收集的目的地寄存器的值的数据结构。可以重复上述步骤，直到获得所有期望的PC值和目标值。

4. 发明授权

US08447957B1 Coprocessor interface architecture and methods of operating the same 有权
标题翻译：协处理器接口架构和操作方法相同
公开(公告)号：US08447957B1
公开(公告)日：2013-05-21
申请号：US11598990
申请日：2006-11-14
申请人： Jorge Ernesto Carrillo , Navaneethan Sundaramoorthy , Sivakumar Velusamy , Ralph D. Wittig , Vasanth Asokan
发明人： Jorge Ernesto Carrillo , Navaneethan Sundaramoorthy , Sivakumar Velusamy , Ralph D. Wittig , Vasanth Asokan
IPC分类号： G06F9/345
CPC分类号： G06F13/1684 , G06F9/3455 , G06F9/3881
摘要： A novel coprocessor interface providing memory access without traversing the main processor, and methods of operating the same. A system includes a bus, a processor circuit, a memory circuit, a multi-channel memory controller, and at least one coprocessor. The processor circuit is coupled to the bus, the multi-channel memory controller is coupled between the bus and the memory circuit, and the coprocessors are coupled to both the processor circuit and the multi-channel memory controller. This circuit arrangement provides dedicated high speed channels for data access between the coprocessors and the memory circuit, without traversing the processor circuit or the bus. Thus, non-standard (e.g., non-sequential) data transfer protocols can be supported. In some embodiments, the system is implemented in a programmable logic device (PLD). The processor circuit can be, for example, a microprocessor included as hard-coded logic in the PLD, or can be implemented using programmable logic elements of the PLD.
摘要翻译：一种新颖的协处理器接口，无需遍历主处理器即可提供存储器访问，以及操作该处理器的方法。系统包括总线，处理器电路，存储器电路，多通道存储器控制器和至少一个协处理器。处理器电路耦合到总线，多通道存储器控制器耦合在总线和存储器电路之间，并且协处理器耦合到处理器电路和多通道存储器控制器两者。该电路装置为协处理器和存储器电路之间的数据访问提供了专用的高速通道，而不用遍历处理器电路或总线。因此，可以支持非标准（例如非顺序）数据传输协议。在一些实施例中，系统在可编程逻辑器件（PLD）中实现。处理器电路可以是例如包括在PLD中作为硬编码逻辑的微处理器，或者可以使用PLD的可编程逻辑元件来实现。

5. 发明授权

US07606694B1 Framework for cycle accurate simulation 有权
标题翻译：循环准确模拟框架
公开(公告)号：US07606694B1
公开(公告)日：2009-10-20
申请号：US11389348
申请日：2006-03-24
申请人： Jorge Ernesto Carrillo , Satish R. Ganesan , Amit Kasat , Sivakumar Velusamy
发明人： Jorge Ernesto Carrillo , Satish R. Ganesan , Amit Kasat , Sivakumar Velusamy
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A system for performing cycle accurate simulation of a circuit design can include a plurality of cycle accurate models, wherein each cycle accurate model is a software object representation of a hardware function, and a scheduler configured to execute each cycle accurate model at clock cycle boundaries determined during a simulation session.
摘要翻译：用于执行电路设计的循环精确模拟的系统可以包括多个周期精确模型，其中每个周期精确模型是硬件功能的软件对象表示，以及调度器，被配置为在确定的时钟周期边界执行每个周期精确模型在模拟会话期间。

6. 发明授权

US07453286B1 Comparator and method of implementing a comparator in a device having programmable logic 有权
标题翻译：比较器和在具有可编程逻辑的器件中实现比较器的方法
公开(公告)号：US07453286B1
公开(公告)日：2008-11-18
申请号：US11788657
申请日：2007-04-19
申请人： Jorge Ernesto Carrillo , Raj Kumar Nagarajan , James M. Pangburn , Navaneethan Sundaramoorthy
发明人： Jorge Ernesto Carrillo , Raj Kumar Nagarajan , James M. Pangburn , Navaneethan Sundaramoorthy
IPC分类号： G06F7/38 , H03K19/173
CPC分类号： G06F7/026
摘要： A method of implementing a comparator in a device having programmable logic is described. The method comprises implementing a first comparison function in a first lookup table; implementing a second comparison function in a second lookup table; and using an output associated with the first comparison function to select an output of the comparator. A device having programmable logic comprising a comparator is also described.
摘要翻译：描述了在具有可编程逻辑的设备中实现比较器的方法。该方法包括在第一查找表中实现第一比较功能; 在第二查找表中实现第二比较功能; 以及使用与第一比较功能相关联的输出来选择比较器的输出。还描述了具有包括比较器的可编程逻辑的装置。

7. 发明授权

US07437701B1 Simulation of a programming language specification of a circuit design 有权
标题翻译：模拟电路设计的编程语言规范
公开(公告)号：US07437701B1
公开(公告)日：2008-10-14
申请号：US11487898
申请日：2006-07-17
申请人： Paulo Luis Dutra , Jorge Ernesto Carrillo
发明人： Paulo Luis Dutra , Jorge Ernesto Carrillo
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： Various approaches for simulating a circuit design are disclosed. In one approach, a first specification of a testbench and a second specification of the circuit design are generated in a hardware description language. The circuit design is synchronous to at least one clock signal. The second specification of the circuit design is automatically translated into a third specification in a general-purpose programming language, and the third specification specifies the behavior of the circuit design at transitions of the at least one clock signal. A fourth specification of an interface between the first specification of the testbench and the third specification of the circuit design is automatically generated. A first behavior of the circuit design is simulated using the first and third specifications linked by the fourth specification and the stimuli from the test bench.
摘要翻译：公开了用于模拟电路设计的各种方法。在一种方法中，以硬件描述语言生成测试台的第一规格和电路设计的第二规范。电路设计与至少一个时钟信号同步。电路设计的第二规范被自动地转换成通用编程语言的第三规范，并且第三规范规定了电路设计在至少一个时钟信号的转变时的行为。自动生成测试台的第一个规范与电路设计的第三个规范之间的界面的第四个规范。电路设计的第一个行为是使用第四个规范链接的第一个和第三个规范以及来自测试台的刺激来模拟的。

8. 发明授权

US07426583B1 Method and circuit for decoding an address of an address space 有权
标题翻译：解码地址空间地址的方法和电路
公开(公告)号：US07426583B1
公开(公告)日：2008-09-16
申请号：US11238431
申请日：2005-09-28
申请人： Paulo L. Dutra , Jorge Ernesto Carrillo , Goran Bilski
发明人： Paulo L. Dutra , Jorge Ernesto Carrillo , Goran Bilski
IPC分类号： G06F3/00 , G06F13/00 , G06F5/00
CPC分类号： G06F12/1081
摘要： Decoding an address in an address space including a plurality of local ranges and a plurality of peripheral ranges is described. Various approaches for decoding an input address include determining decoder address bits of the address space that distinguish local ranges from each other and that distinguish local ranges from peripheral ranges. The local and peripheral ranges are interleaved and have a plurality of sizes. The number of decoder address bits is less than the number of address bits in the address space and less than the number of local ranges plus the number of peripheral ranges. Using the decoder address bits of an input address, it is determined whether the input address is within a portion of the address space that includes one of the local ranges and does not include any of the peripheral ranges nor the local ranges other than the one of the local ranges.
摘要翻译：描述包括多个局部范围和多个外围范围的地址空间中的地址的解码。用于对输入地址进行解码的各种方法包括确定区分本地范围的地址空间的解码器地址位，并且区分本地范围与周边范围。本地和外围范围是交错的并且具有多个尺寸。解码器地址位的数量小于地址空间中的地址位数，小于本地范围的数量以及周边数量。使用输入地址的解码器地址位，确定输入地址是否在包括本地范围之一的地址空间的一部分内，并且不包括任何外围范围和除了当地范围。

9. 发明授权

US07315803B1 Verification environment creation infrastructure for bus-based systems and modules 有权
标题翻译：基于总线的系统和模块的验证环境创建基础架构
公开(公告)号：US07315803B1
公开(公告)日：2008-01-01
申请号：US11055275
申请日：2005-02-10
申请人： Jorge Ernesto Carrillo , Paulo Luis Dutra
发明人： Jorge Ernesto Carrillo , Paulo Luis Dutra
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5022 , G01R31/318364 , G01R31/318378
摘要： A method of building a verification environment within a software-based development tool for a programmable logic device can include determining an interface description for a bus functional model. The method further can include creating a hardware specification for the programmable logic device. The hardware specification can reference the bus functional model and at least one bus-based module interacting with the bus functional model. The verification environment for the programmable logic device can be automatically generated according to the interface description and the hardware specification.
摘要翻译：在可编程逻辑设备的基于软件的开发工具内构建验证环境的方法可以包括确定总线功能模型的接口描述。该方法还可以包括为可编程逻辑器件创建硬件规范。硬件规范可以引用总线功能模型和至少一个基于总线的模块与总线功能模型交互。可编程逻辑器件的验证环境可以根据接口描述和硬件规格自动生成。

10. 发明授权

US06963966B1 Accumulator-based load-store CPU architecture implementation in a programmable logic device 有权
标题翻译：基于累加器的加载存储CPU架构在可编程逻辑器件中的实现
公开(公告)号：US06963966B1
公开(公告)日：2005-11-08
申请号：US10209516
申请日：2002-07-30
申请人： Jorge Ernesto Carrillo
发明人： Jorge Ernesto Carrillo
IPC分类号： G06F15/78 , G06F17/50
CPC分类号： G06F15/7867
摘要： Methods and structures for efficiently implementing an accumulator-based load-store CPU architecture in a programmable logic device (PLD). The PLD includes programmable logic blocks, each logic block including function generators that can be optionally programmed to function as lookup tables or as RAM blocks. Each element of the CPU is implemented using these logic blocks, including an instruction register, an accumulator pointer, a register file, and an operation block. The register file is implemented using function generators configured as RAM blocks. This implementation eliminates the need for time-consuming accesses to an off-chip register file or to a dedicated RAM block.
摘要翻译：在可编程逻辑器件（PLD）中有效实施基于累加器的加载存储CPU架构的方法和结构。 PLD包括可编程逻辑块，每个逻辑块包括功能发生器，其可选地被编程为用作查找表或RAM块。使用这些逻辑块来实现CPU的每个元件，包括指令寄存器，累加器指针，寄存器文件和操作块。寄存器文件是使用配置为RAM块的函数发生器实现的。该实现消除了对片外寄存器文件或专用RAM块的耗时访问的需要。

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