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1. 发明申请

US20090146700A1 DUTY RATIO CORRECTION CIRCUIT 审中-公开
标题翻译：占空比校正电路
公开(公告)号：US20090146700A1
公开(公告)日：2009-06-11
申请号：US12178475
申请日：2008-07-23
申请人： Yong Ju Kim , Kun Woo Park , Kyung Hoon Kim , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee
发明人： Yong Ju Kim , Kun Woo Park , Kyung Hoon Kim , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee
IPC分类号： H03L7/00
CPC分类号： H03L7/0814 , H03K5/1565 , H03L7/07
摘要： A duty ratio correction circuit including a reference clock generation block configured to generate first and second reference clocks that synchronize with rising and falling edges of an external clock and have a primarily corrected duty ratio, and a duty ratio adjustment block for generating first and second internal clocks in response to the first and second reference clocks, and secondarily correcting a duty ratio of the first and second reference clocks by adjusting phases of the first and second reference clocks by means of plural digital control signals generated according to phase difference between the first and second internal clocks.
摘要翻译：一种占空比校正电路，包括：参考时钟产生模块，被配置为产生与外部时钟的上升沿和下降沿同步并具有主要校正的占空比的第一和第二参考时钟;以及占空比调整块，用于产生第一和第二内部响应于第一和第二参考时钟的时钟，并且通过根据根据第一和第二参考时钟的第一和第二参考时钟之间的相位差产生的多个数字控制信号来调整第一和第二参考时钟的占空比，第二个内部时钟。

2. 发明申请

US20090128192A1 DATA RECEIVER OF SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR CONTROLLING THE SAME 失效
标题翻译：半导体集成电路的数据接收器及其控制方法
公开(公告)号：US20090128192A1
公开(公告)日：2009-05-21
申请号：US12176215
申请日：2008-07-18
申请人： Hyung Soo Kim , Kun Woo Park , Yong Ju Kim , Hee Woong Song , Ic Su Oh , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee
发明人： Hyung Soo Kim , Kun Woo Park , Yong Ju Kim , Hee Woong Song , Ic Su Oh , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee
IPC分类号： G11C7/00 , H03K19/00
CPC分类号： G11C7/1078 , G11C7/1084 , G11C7/1087
摘要： A data receiver of a semiconductor integrated circuit includes an amplifier that outputs an amplified signal by detecting and amplifying received data using equalization function according to feedback data, a detecting unit that detects a period when data is not received in the amplifier and outputs a detecting signal, and an equalization function control unit that stops the equalization function of the amplifier in response to the detecting signal.
摘要翻译：半导体集成电路的数据接收器包括：放大器，其通过根据反馈数据使用均衡功能检测和放大接收数据来输出放大信号;检测单元，其检测在放大器中未接收到数据的周期，并输出检测信号以及均衡功能控制单元，其响应于检测信号停止放大器的均衡功能。

3. 发明申请

US20100090726A1 DATA RECEIVER OF SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
标题翻译：半导体集成电路的数据接收器
公开(公告)号：US20100090726A1
公开(公告)日：2010-04-15
申请号：US12636922
申请日：2009-12-14
申请人： Hyung Soo Kim , Kun Woo Park , Yong Ju Kim , Hee Woong Song , Ic Su Oh , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee
发明人： Hyung Soo Kim , Kun Woo Park , Yong Ju Kim , Hee Woong Song , Ic Su Oh , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee
IPC分类号： G01R19/00
CPC分类号： G11C7/1078 , G11C7/1084 , G11C7/1087
摘要： A data receiver of a semiconductor integrated circuit is configured to detect received data using an equalization function, wherein the data receiver is configured to stop the equalization function during a period in which the data is not received.
摘要翻译：半导体集成电路的数据接收器被配置为使用均衡功能检测接收到的数据，其中数据接收器被配置为在未接收到数据的时段期间停止均衡功能。

4. 发明申请

US20090149142A1 RECEIVER CIRCUIT 有权
标题翻译：接收电路
公开(公告)号：US20090149142A1
公开(公告)日：2009-06-11
申请号：US12179486
申请日：2008-07-24
申请人： Tae Jin Hwang , Kun Woo Park , Yong Ju Kim , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Hae Rang Choi , Ji Wang Lee , Jae Min Jang
发明人： Tae Jin Hwang , Kun Woo Park , Yong Ju Kim , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Hae Rang Choi , Ji Wang Lee , Jae Min Jang
IPC分类号： G06F3/033
CPC分类号： G06F13/4072
摘要： A receiver circuit is capable of improving its operating characteristics. The receiver circuit includes a variable converter configured to output off-set control voltages in a first output range in a first operation mode and output the off-set control voltages in a second output range in a second operation mode according to a test mode activation signal, and a sense amplifier configured to sense input data based on a sensitivity, wherein the sensitivity is controlled by the off-set control voltages.
摘要翻译：接收机电路能够改善其操作特性。接收器电路包括可变转换器，其被配置为在第一操作模式中在第一输出范围中输出偏移控制电压，并且根据测试模式激活信号在第二操作模式中将偏移控制电压输出到第二输出范围以及感测放大器，被配置为基于灵敏度来感测输入数据，其中灵敏度由偏移控制电压控制。

5. 发明申请

US20090129459A1 DATA RECEIVER OF SEMICONDUCTOR INTEGRATED CIRCUIT 失效
标题翻译：半导体集成电路的数据接收器
公开(公告)号：US20090129459A1
公开(公告)日：2009-05-21
申请号：US12177829
申请日：2008-07-22
申请人： Hyung Soo Kim , Kun Woo Park , Yong Ju Kim , Hee Woong Song , Ic Su Oh , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee
发明人： Hyung Soo Kim , Kun Woo Park , Yong Ju Kim , Hee Woong Song , Ic Su Oh , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee
IPC分类号： H03K5/159
CPC分类号： H03K19/09425
摘要： A semiconductor integrated circuit equipped with an equalizer which has a circuit structure simpler than that of a related equalizer according to an FFE scheme or a DFE scheme and is capable of preventing a noise component from being amplified. The data receiver includes a plurality of receiver units, wherein each receiver unit includes a plurality of level detectors which detect different levels, and an encoder, in which the level detectors receive data according to a clock signal having a predetermined phase difference and perform an amplification operation including an equalization function based on feedback data, thereby outputting an amplification signal, and wherein level detectors of one receiver unit receive an amplification signal, as the feedback data, from level detectors of another receiver unit that receives a first clock signal having a phase more advanced than a phase of a second clock signal received in one receiver unit.
摘要翻译：一种配备有均衡器的半导体集成电路，其具有比根据FFE方案或DFE方案的相关均衡器的电路结构简单的电路结构，并且能够防止噪声分量被放大。数据接收机包括多个接收机单元，其中每个接收机单元包括检测不同电平的多个电平检测器和编码器，其中电平检测器根据具有预定相位差的时钟信号接收数据并执行放大操作包括基于反馈数据的均衡功能，从而输出放大信号，并且其中一个接收器单元的电平检测器从另一接收器单元的电平检测器接收作为反馈数据的放大信号，该接收器单元接收具有相位的第一时钟信号比在一个接收机单元中接收的第二时钟信号的相位更先进。

6. 发明申请

US20090067278A1 DATA OUTPUT CIRCUIT FOR SEMICONDUCTOR MEMORY APPARATUS 有权
标题翻译：半导体存储器的数据输出电路
公开(公告)号：US20090067278A1
公开(公告)日：2009-03-12
申请号：US12169568
申请日：2008-07-08
申请人： Hae Rang Choi , Kun Woo Park , Yong Ju Kim , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Ji Wang Lee
发明人： Hae Rang Choi , Kun Woo Park , Yong Ju Kim , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Ji Wang Lee
IPC分类号： G11C8/08
CPC分类号： G11C7/1051 , G11C7/1057 , G11C29/028 , G11C29/1201 , G11C29/50
摘要： A data output circuit for a semiconductor memory apparatus includes a driver control signal generating unit that has a plurality of control signal generating units, each of which generates a driver unit control signal in response to a test signal during a test, and generates the driver unit control signal according to whether or not a fuse is cut after the test is completed, a first driver that has a plurality of driver units, each of which is activated in response to the driver unit control signal to drive a first data signal as an input signal and to output the driven first data signal to an output node, a signal combining unit that generates a first driver control signal in response to the driver unit control signal and an enable signal, and a second driver that has a plurality of driver units, each of which is activated in response to the first driver control signal to drive a second data signal as an input signal and to output the driven second data signal to the output node, and the number of driver units being two or more times as much as the number of driver units in the first driver. A voltage level on the output node is the voltage level of an output signal.
摘要翻译：一种用于半导体存储装置的数据输出电路，包括具有多个控制信号生成单元的驱动器控制信号生成单元，每个控制信号生成单元响应于测试期间的测试信号生成驱动单元控制信号，并且生成驱动单元根据在测试完成之后是否切断熔丝的控制信号，具有多个驱动单元的第一驱动器，每个驱动器单元响应于驱动单元控制信号被激活以驱动第一数据信号作为输入信号并将驱动的第一数据信号输出到输出节点;响应于驱动单元控制信号和使能信号产生第一驱动器控制信号的信号组合单元，以及具有多个驱动器单元的第二驱动器，其中的每一个响应于第一驱动器控制信号被激活，以驱动第二数据信号作为输入信号，并将驱动的第二数据信号输出到输出节点;以及驱动器单元的数量是第一驱动器中的驱动器单元的数量的两倍或更多倍。输出节点上的电压电平是输出信号的电压电平。

7. 发明申请

US20090045862A1 CLOCK GENERATING CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS 审中-公开
标题翻译：半导体存储器的时钟发生电路
公开(公告)号：US20090045862A1
公开(公告)日：2009-02-19
申请号：US12167066
申请日：2008-07-02
申请人： Yong Ju Kim , Kun Woo Park , Dae Han Kwon , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee
发明人： Yong Ju Kim , Kun Woo Park , Dae Han Kwon , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee
IPC分类号： H03K4/00
CPC分类号： H03K5/151
摘要： A clock generating circuit of a semiconductor memory apparatus includes a phase splitter that delays a clock to generate a delayed clock and inverts the clock to generate an inverted clock, and a clock buffer that buffers the delayed clock and the inverted clock and outputs a rising clock and a falling clock.
摘要翻译：半导体存储装置的时钟产生电路包括：相位分离器，其延迟时钟以产生延迟的时钟并使时钟反相以产生反相时钟;以及时钟缓冲器，缓冲延迟时钟和反相时钟，并输出上升时钟和一个下降的时钟。

8. 发明授权

US08045647B2 Low power, high speed receiver circuit for use in a semiconductor integrated circuit 失效
标题翻译：用于半导体集成电路的低功率，高速接收电路
公开(公告)号：US08045647B2
公开(公告)日：2011-10-25
申请号：US12170254
申请日：2008-07-09
申请人： Ic Su Oh , Kun Woo Park , Yong Ju Kim , Hee Woong Song , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee
发明人： Ic Su Oh , Kun Woo Park , Yong Ju Kim , Hee Woong Song , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee
IPC分类号： H03K9/00 , H04L27/00
CPC分类号： G11C7/1051 , G11C7/062 , G11C7/1069 , G11C11/56 , G11C27/026 , G11C2211/5634 , G11C2211/5642 , H04L25/0272 , H04L25/061 , H04L25/4919
摘要： A receiver circuit according to the invention includes a first phase transmission unit that is synchronized with a first clock, detects input data according to a plurality of detection levels, and transmits a first output signal, a first discharging control unit that controls a second phase transmission unit in response to the first output signal and adjusts the transmission speed of the second phase transmission unit by changing a node potential where an output of the second phase transmission is determined, and the second phase transmission unit that is synchronized with a second clock, detects the input data according to an output of the first discharging control unit, and transmits a second output signal.
摘要翻译：根据本发明的接收机电路包括与第一时钟同步的第一相位传输单元，根据多个检测电平检测输入数据，并发送第一输出信号;第一放电控制单元，其控制第二相位传输单元，响应于第一输出信号，并且通过改变确定第二相位传输的输出的节点电位来调整第二相位传输单元的传输速度，并且与第二时钟同步的第二相位传输单元检测所述输入数据根据所述第一放电控制单元的输出，并发送第二输出信号。

9. 发明申请

US20090128214A1 DATA RECEIVER OF SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
标题翻译：半导体集成电路的数据接收器
公开(公告)号：US20090128214A1
公开(公告)日：2009-05-21
申请号：US12177023
申请日：2008-07-21
申请人： Hyung Soo Kim , Kun Woo Park , Yong Ju Kim , Hee Woong Song , Ic Su Oh , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee
发明人： Hyung Soo Kim , Kun Woo Park , Yong Ju Kim , Hee Woong Song , Ic Su Oh , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee
IPC分类号： H03L5/00
CPC分类号： G11C7/1078 , G11C7/1084 , G11C7/1087
摘要： A data receiver includes a plurality of amplifiers for receiving data in response to clock signals having a predetermined phase difference, and amplifying the received data by performing an equalization function based on feedback data, thereby outputting amplification signals, and a plurality of latches for latching output of the amplifiers, respectively. One amplifier receives the amplification signal, as feedback data, from another amplifier receiving a clock signal having a phase more advanced than a phase of a clock signal received in the one amplifier.
摘要翻译：数据接收机包括响应于具有预定相位差的时钟信号而接收数据的多个放大器，并且通过基于反馈数据执行均衡功能来放大接收数据，从而输出放大信号，以及多个锁存器用于锁存输出的放大器。一个放大器接收作为反馈数据的放大信号，来自另一个放大器接收时钟信号，该时钟信号的相位比在一个放大器中接收的时钟信号的相位更先进。

10. 发明申请

US20090116596A1 LOW POWER, HIGH SPEED RECEIVER CIRCUIT FOR USE IN A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
标题翻译：低功率，高速接收电路，用于半导体集成电路
公开(公告)号：US20090116596A1
公开(公告)日：2009-05-07
申请号：US12170254
申请日：2008-07-09
申请人： Ic Su Oh , Kun Woo Park , Yong Ju Kim , Hee Woong Song , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee
发明人： Ic Su Oh , Kun Woo Park , Yong Ju Kim , Hee Woong Song , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee
IPC分类号： H04L7/00
CPC分类号： G11C7/1051 , G11C7/062 , G11C7/1069 , G11C11/56 , G11C27/026 , G11C2211/5634 , G11C2211/5642 , H04L25/0272 , H04L25/061 , H04L25/4919
摘要： A receiver circuit according to the invention includes a first phase transmission unit that is synchronized with a first clock, detects input data according to a plurality of detection levels, and transmits a first output signal, a first discharging control unit that controls a second phase transmission unit in response to the first output signal and adjusts the transmission speed of the second phase transmission unit by changing a node potential where an output of the second phase transmission is determined, and the second phase transmission unit that is synchronized with a second clock, detects the input data according to an output of the first discharging control unit, and transmits a second output signal.
摘要翻译：根据本发明的接收机电路包括与第一时钟同步的第一相位传输单元，根据多个检测电平检测输入数据，并发送第一输出信号;第一放电控制单元，其控制第二相位传输单元，响应于第一输出信号，并且通过改变确定第二相位传输的输出的节点电位来调整第二相位传输单元的传输速度，并且与第二时钟同步的第二相位传输单元检测所述输入数据根据所述第一放电控制单元的输出，并发送第二输出信号。

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