专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20120137051A1 MEMORY DEVICE CONFIGURED TO EXECUTE PLURAL ACCESS COMMANDS IN PARALLEL AND MEMORY ACCESS METHOD THEREFOR 失效
标题翻译：配置为执行并行访问的访问命令的存储器件和存储器访问方法
公开(公告)号：US20120137051A1
公开(公告)日：2012-05-31
申请号：US13226271
申请日：2011-09-06
申请人： Yoko Masuo , Taichiro Yamanaka , Hironobu Miyamoto
发明人： Yoko Masuo , Taichiro Yamanaka , Hironobu Miyamoto
IPC分类号： G06F12/02
CPC分类号： G06F13/16
摘要： According to one embodiment, a memory device includes a memory, a memory interface, a command generator, an access command returning module and a command progress manager. The memory interface accesses the memory in parallel in accordance with access commands. The command generator speculatively issues access commands to the memory interface. The access command returning module returns access commands already issued to the memory interface and unexecuted at a time of occurrence of an error, through corresponding purge responses. The command progress manager updates command progress management information such that the command progress management information indicates the oldest one of the unexecuted access commands. The command generator reissues the returned unexecuted access commands to the memory interface based on the updated command progress management information.
摘要翻译：根据一个实施例，存储器装置包括存储器，存储器接口，命令发生器，访问命令返回模块和命令进度管理器。存储器接口根据访问命令并行访问存储器。命令生成器推测地向存储器接口发出访问命令。访问命令返回模块返回已发送到存储器接口的访问命令，并通过相应的清除响应在发生错误时执行。命令进度管理器更新命令进度管理信息，使得命令进度管理信息指示未执行的访问命令中最早的一个。命令生成器基于更新的命令进度管理信息将返回的未执行的访问命令重新发送到存储器接口。

2. 发明申请

US20140025863A1 DATA STORAGE DEVICE, MEMORY CONTROL METHOD, AND ELECTRONIC DEVICE WITH DATA STORAGE DEVICE 有权
标题翻译：数据存储装置，存储器控制方法和具有数据存储装置的电子装置
公开(公告)号：US20140025863A1
公开(公告)日：2014-01-23
申请号：US13720356
申请日：2012-12-19
申请人： Taichiro Yamanaka , Yoko Masuo , Hironobu Miyamoto
发明人： Taichiro Yamanaka , Yoko Masuo , Hironobu Miyamoto
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F2212/7205
摘要： According to one embodiment, a data storage device includes a first controller, a second controller, and a third controller. The first controller performs a control operation of writing data of a first data unit to a storage area in a flash memory and reading the data of the first data unit from the storage area. The second controller carries out migration processing of measuring a data amount of valid data stored in storage areas of a second data unit that is a data erase processing unit.
摘要翻译：根据一个实施例，数据存储设备包括第一控制器，第二控制器和第三控制器。第一控制器执行将第一数据单元的数据写入闪速存储器中的存储区域并从存储区域读取第一数据单元的数据的控制操作。第二控制器执行迁移处理，测量存储在作为数据擦除处理单元的第二数据单元的存储区域中的有效数据的数据量。

3. 发明申请

US20120233382A1 DATA STORAGE APPARATUS AND METHOD FOR TABLE MANAGEMENT 审中-公开
标题翻译：数据存储装置和表管理方法
公开(公告)号：US20120233382A1
公开(公告)日：2012-09-13
申请号：US13304188
申请日：2011-11-23
申请人： Taichiro Yamanaka , Yoko Masuo , Hironobu Miyamoto
发明人： Taichiro Yamanaka , Yoko Masuo , Hironobu Miyamoto
IPC分类号： G06F12/00
CPC分类号： G11B20/18 , G06F3/0679 , G11B27/105 , G11B27/322 , G11B2220/60
摘要： According to one embodiment, a data storage apparatus includes a first memory configured to store a first management table, a second memory configured to store a second management table, a counter table memory, and a controller. The first management table has address data representing a storage position of data stored in a flash memory. The second memory has address data representing valid data included in the data stored in the flash memory. The counter table memory stores a counter table showing the count value of valid data in units of addresses. The controller is configured to refer to the first management table, to compare the number of data valid in units of addresses acquired by referring to the first management table, and to perform a matching check process for determining matching between the first and second management tables from a result of the comparison.
摘要翻译：根据一个实施例，数据存储装置包括被配置为存储第一管理表的第一存储器，被配置为存储第二管理表的第二存储器，计数器表存储器和控制器。第一管理表具有表示存储在闪速存储器中的数据的存储位置的地址数据。第二存储器具有表示存储在闪速存储器中的数据中包含的有效数据的地址数据。计数器表存储器存储以地址为单位的有效数据的计数值的计数器表。控制器被配置为参考第一管理表，以通过参考第一管理表来获取的地址单元中的有效数据的数量进行比较，并且执行用于确定第一和第二管理表之间的匹配的匹配检查处理比较的结果。

4. 发明授权

US08688898B2 Memory device configured to execute plural access commands in parallel and memory access method therefor 失效
标题翻译：被配置为并行地执行多个访问命令的存储器件及其存储器访问方法
公开(公告)号：US08688898B2
公开(公告)日：2014-04-01
申请号：US13226271
申请日：2011-09-06
申请人： Yoko Masuo , Taichiro Yamanaka , Hironobu Miyamoto
发明人： Yoko Masuo , Taichiro Yamanaka , Hironobu Miyamoto
IPC分类号： G06F12/00
CPC分类号： G06F13/16
摘要： According to one embodiment, a memory device includes a memory, a memory interface, a command generator, an access command returning module and a command progress manager. The memory interface accesses the memory in parallel in accordance with access commands. The command generator speculatively issues access commands to the memory interface. The access command returning module returns access commands already issued to the memory interface and unexecuted at a time of occurrence of an error, through corresponding purge responses. The command progress manager updates command progress management information such that the command progress management information indicates the oldest one of the unexecuted access commands. The command generator reissues the returned unexecuted access commands to the memory interface based on the updated command progress management information.
摘要翻译：根据一个实施例，存储器装置包括存储器，存储器接口，命令发生器，访问命令返回模块和命令进度管理器。存储器接口根据访问命令并行访问存储器。命令生成器推测地向存储器接口发出访问命令。访问命令返回模块返回已发送到存储器接口的访问命令，并通过相应的清除响应在发生错误时执行。命令进度管理器更新命令进度管理信息，使得命令进度管理信息指示未执行的访问命令中最早的一个。命令生成器基于更新的命令进度管理信息将返回的未执行的访问命令重新发送到存储器接口。

5. 发明授权

US08689079B2 Memory device having multiple channels and method for accessing memory in the same 失效
标题翻译：具有多个通道的存储器件和用于访问存储器的方法
公开(公告)号：US08689079B2
公开(公告)日：2014-04-01
申请号：US13333345
申请日：2011-12-21
申请人： Yoko Masuo , Taichiro Yamanaka , Hironobu Miyamoto
发明人： Yoko Masuo , Taichiro Yamanaka , Hironobu Miyamoto
IPC分类号： H03M13/00
CPC分类号： G06F11/141
摘要： According to one embodiment, a command generator sequentially and speculatively issues channel-by-channel access commands to a memory interface in a predetermined access process. A purger returns a series of unexecuted already-issued access commands using a purge response if an error occurs in any of memory accesses via a plurality of channels. A command progress manager updates command progress information such that the command progress on each of the plurality of channels returns to a position specified in an oldest access command of a series of the returned access commands issued to the channel. The command generator issues the channel-by-channel access commands including the oldest access command to the memory interface based on the updated command progress information.
摘要翻译：根据一个实施例，命令发生器在预定的访问过程中顺序地并且推测地向存储器接口发送逐个通道访问命令。如果在通过多个通道的任何存储器访问中发生错误，则清除器使用清除响应返回一系列未执行的已发出的访问命令。命令进度管理器更新命令进度信息，使得多个通道中的每个通道上的命令进程返回到发布到通道的一系列返回的访问命令的最早访问命令中指定的位置。命令生成器根据更新的命令进度信息发出逐个通道访问命令，包括对存储器接口的最早访问命令。

6. 发明申请

US20120221921A1 MEMORY DEVICE HAVING MULTIPLE CHANNELS AND METHOD FOR ACCESSING MEMORY IN THE SAME 失效
标题翻译：具有多个通道的存储器件和用于存储器件的存储器
公开(公告)号：US20120221921A1
公开(公告)日：2012-08-30
申请号：US13333345
申请日：2011-12-21
申请人： Yoko MASUO , Taichiro Yamanaka , Hironobu Miyamoto
发明人： Yoko MASUO , Taichiro Yamanaka , Hironobu Miyamoto
IPC分类号： G06F11/08 , G06F12/00
CPC分类号： G06F11/141
摘要： According to one embodiment, a command generator sequentially and speculatively issues channel-by-channel access commands to a memory interface in a predetermined access process. A purger returns a series of unexecuted already-issued access commands using a purge response if an error occurs in any of memory accesses via a plurality of channels. A command progress manager updates command progress information such that the command progress on each of the plurality of channels returns to a position specified in an oldest access command of a series of the returned access commands issued to the channel. The command generator issues the channel-by-channel access commands including the oldest access command to the memory interface based on the updated command progress information.
摘要翻译：根据一个实施例，命令发生器在预定的访问过程中顺序地并且推测地向存储器接口发送逐个通道访问命令。如果在通过多个通道的任何存储器访问中发生错误，则清除器使用清除响应返回一系列未执行的已发出的访问命令。命令进度管理器更新命令进度信息，使得多个通道中的每个通道上的命令进程返回到发布到通道的一系列返回的访问命令的最早访问命令中指定的位置。命令生成器根据更新的命令进度信息发出逐个通道访问命令，包括对存储器接口的最早访问命令。

7. 发明授权

US09384124B2 Data storage device, memory control method, and electronic device with data storage device 有权
标题翻译：数据存储装置，存储器控制方法和具有数据存储装置的电子装置
公开(公告)号：US09384124B2
公开(公告)日：2016-07-05
申请号：US13720356
申请日：2012-12-19
申请人： Taichiro Yamanaka , Yoko Masuo , Hironobu Miyamoto
发明人： Taichiro Yamanaka , Yoko Masuo , Hironobu Miyamoto
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F2212/7205
摘要： According to one embodiment, a data storage device includes a first controller, a second controller, and a third controller. The first controller performs a control operation of writing data of a first data unit to a storage area in a flash memory and reading the data of the first data unit from the storage area. The second controller carries out migration processing of measuring a data amount of valid data stored in storage areas of a second data unit that is a data erase processing unit.
摘要翻译：根据一个实施例，数据存储设备包括第一控制器，第二控制器和第三控制器。第一控制器执行将第一数据单元的数据写入闪速存储器中的存储区域并从存储区域读取第一数据单元的数据的控制操作。第二控制器执行迁移处理，测量存储在作为数据擦除处理单元的第二数据单元的存储区域中的有效数据的数据量。

8. 发明授权

US08930614B2 Data storage apparatus and method for compaction processing 有权
标题翻译：用于压实处理的数据存储装置和方法
公开(公告)号：US08930614B2
公开(公告)日：2015-01-06
申请号：US13560486
申请日：2012-07-27
申请人： Yoko Masuo , Yoshimasa Aoyama , Hironobu Miyamoto
发明人： Yoko Masuo , Yoshimasa Aoyama , Hironobu Miyamoto
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F2212/7205
摘要： According to one embodiment, a data storage apparatus includes a flash memory and a controller. The controller includes a compaction processor. The compaction processor performs the compaction processing on the flash memory, to dynamically set a range of compaction processing targets based on a number of available blocks and an amount of valid data in each of the blocks, and to search the range of compaction processing targets for blocks each with a relatively small amount of valid data as the target blocks for the compaction processing.
摘要翻译：根据一个实施例，数据存储装置包括闪速存储器和控制器。控制器包括压缩处理器。压缩处理器对闪速存储器执行压缩处理，基于可用块的数量和每个块中的有效数据量来动态地设置压缩处理目标的范围，并且搜索压缩处理目标的范围阻止每个具有相对少量的有效数据作为压缩处理的目标块。

9. 发明授权

US08671257B2 Memory system having multiple channels and method of generating read commands for compaction in memory system 失效
标题翻译：具有多个通道的存储器系统和在存储器系统中产生用于压缩的读取命令的方法
公开(公告)号：US08671257B2
公开(公告)日：2014-03-11
申请号：US13422947
申请日：2012-03-16
申请人： Yoko Masuo , Wataru Okamoto , Hironobu Miyamoto
发明人： Yoko Masuo , Wataru Okamoto , Hironobu Miyamoto
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F2212/401 , G06F2212/7204
摘要： According to one embodiment, a valid-cluster search module searches valid clusters included in first blocks, in each of channels, for compaction. A read command generator generates read commands used to read, in parallel, valid clusters to be migrated to a second block. The valid clusters searched in each of the channels comprise the valid clusters to be migrated. The valid clusters to be migrated correspond to a number of clusters simultaneously written to the second block and to a second number of channels in a first number of channels. A determination module determines the second number of channels corresponding to read commands to be generated next based on a situation of issuance of the read commands.
摘要翻译：根据一个实施例，有效群集搜索模块搜索包括在每个信道中的第一块中的有效簇以用于压缩。读命令生成器生成用于并行读取要迁移到第二块的有效集群的读命令。在每个通道中搜索的有效集群包括要迁移的有效集群。要迁移的有效簇对应于同时写入第二块的多个簇和第一数量的信道中的第二数量的信道。确定模块基于读取命令的发布的情况来确定与下一个要生成的读取命令相对应的通道的第二数量。

10. 发明申请

US20120054418A1 STORAGE CONTROLLER, STORAGE DEVICE, AND DATA TRANSFER CONTROL METHOD 有权
标题翻译：存储控制器，存储设备和数据传输控制方法
公开(公告)号：US20120054418A1
公开(公告)日：2012-03-01
申请号：US13154203
申请日：2011-06-06
申请人： Yoko Masuo , Hironobu Miyamoto , Wataru Okamoto
发明人： Yoko Masuo , Hironobu Miyamoto , Wataru Okamoto
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F2212/7211
摘要： According to one embodiment, a storage controller includes a condition storage, a determination module, a wear-leveling block retainer, and a data transfer controller. The condition storage is provided in a storage including a plurality of blocks, and stores block condition information including at least one of erasure time information indicating when data is erased last time and erasure count information indicating the number of times data is erased. The determination module determines whether there is a block that requires wear leveling based on the block condition information. The wear-leveling block retainer retains block identification information that identifies a block determined to require wear leveling. The data transfer controller performs compaction to transfer data stored in blocks of the storage for collecting the data in a block, and, when the block identification information is retained, transfers data stored in the block identified by the block identification information.
摘要翻译：根据一个实施例，存储控制器包括条件存储器，确定模块，磨损均衡块保持器和数据传输控制器。条件存储被提供在包括多个块的存储器中，并且存储包括指示上次擦除数据的擦除时间信息中的至少一个的块条件信息，以及指示擦除次数数据的擦除计数信息。确定模块基于块条件信息确定是否存在需要磨损均衡的块。磨损平整块保持器保持块识别信息，其识别确定为需要磨损均匀化的块。数据传输控制器执行压缩以将存储在存储器块中的数据传送到块中以收集数据，并且当块识别信息被保留时，传送存储在由块识别信息识别的块中的数据。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式