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1. 发明申请

US20080122060A1 SEMICONDUCTOR DEVICE INCLUDING CORROSION RESISTANT WIRING STRUCTURE 审中-公开
标题翻译：包括耐腐蚀接线结构的半导体器件
公开(公告)号：US20080122060A1
公开(公告)日：2008-05-29
申请号：US11558056
申请日：2006-11-09
申请人： Yoichi NOGAMI , Koichi FUJITA
发明人： Yoichi NOGAMI , Koichi FUJITA
IPC分类号： H01L23/48
CPC分类号： H01L24/11 , H01L24/13 , H01L2224/05001 , H01L2224/05022 , H01L2224/05027 , H01L2224/0508 , H01L2224/05166 , H01L2224/05572 , H01L2224/05644 , H01L2224/11 , H01L2224/1147 , H01L2224/13 , H01L2224/13099 , H01L2224/16 , H01L2924/01006 , H01L2924/01019 , H01L2924/01022 , H01L2924/01033 , H01L2924/01041 , H01L2924/01042 , H01L2924/01045 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/04953 , H01L2924/00 , H01L2924/00014
摘要： A semiconductor device packaged in a non-hermetic package includes a semiconductor substrate; a wiring metal film on the semiconductor substrate; a plating power supply film on the wiring metal film; an Au plated portion on the plating power supply film; a metal film covering the Au plated portion; and an insulating protective film covering the metal film. The metal film is a material having corrosion resistance properties such that a potential-pH diagram of the metal material predominantly includes a corrosion-free region and a passive region and either does not include a corrosion region or includes a very small corrosion region, the potential-pH diagram showing the effects of electrical potential and pH on corrosion of the metal material.
摘要翻译：封装在非密封封装中的半导体器件包括半导体衬底; 半导体衬底上的布线金属膜; 布线金属膜上的电镀电源膜; 电镀膜上的镀Au部分; 覆盖Au镀层的金属膜; 以及覆盖金属膜的绝缘保护膜。金属膜是具有耐腐蚀性的材料，使得金属材料的电势 - pH图主要包括无腐蚀区域和无源区域，或者不包括腐蚀区域或包括非常小的腐蚀区域，电位 -pH图显示了电势和pH对金属材料腐蚀的影响。

2. 发明申请

US20120217557A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120217557A1
公开(公告)日：2012-08-30
申请号：US13460962
申请日：2012-05-01
申请人： Yoichi NOGAMI
发明人： Yoichi NOGAMI
IPC分类号： H01L29/78
CPC分类号： H01L29/8128
摘要： A semiconductor device includes: a semiconductor substrate of a compound semiconductor material; a buffer layer, a channel layer, and a Schottky junction forming layer sequentially disposed on the semiconductor substrate, the buffer layer, the channel layer, and the Schottky junction forming layer each being compound semiconductor materials; a source electrode and a drain electrode located on the Schottky junction forming layer; and a gate electrode disposed between the source and drain electrodes and forming a Schottky junction with the Schottky junction forming layer. The carrier density in the channel layer varies with distance from a top surface of the channel layer and is inversely proportional to the third power of depth into the channel layer from the top surface of the channel layer. The buffer layer has a lower electron affinity than the channel layer and is a different compound semiconductor material from the channel layer.
摘要翻译：半导体器件包括：化合物半导体材料的半导体衬底; 顺序地设置在半导体衬底上的缓冲层，沟道层和肖特基结形成层，缓冲层，沟道层和肖特基结形成层均为化合物半导体材料; 位于肖特基结形成层上的源电极和漏电极; 以及设置在源极和漏极之间并与肖特基结形成层形成肖特基结的栅电极。沟道层中的载流子密度随距离沟道层顶表面的距离而变化，并且与沟道层顶表面的沟道层深度的第三次方成反比。缓冲层具有比沟道层更低的电子亲和力，并且是与沟道层不同的化合物半导体材料。

3. 发明申请

US20120007153A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120007153A1
公开(公告)日：2012-01-12
申请号：US13238038
申请日：2011-09-21
申请人： Yoichi NOGAMI
发明人： Yoichi NOGAMI
IPC分类号： H01L29/812
CPC分类号： H01L29/8128
摘要： A semiconductor device includes: a compound semiconductor substrate; a buffer layer, a channel layer, and a Schottky junction forming layer sequentially disposed on the compound semiconductor substrate, the buffer layer, the channel layer, and the Schottky junction forming layer each being compound semiconductor materials; a source electrode and a drain electrode located on the Schottky junction forming layer; and a gate electrode disposed between the source and drain electrodes and forming a Schottky junction with the Schottky junction forming layer. The dopant impurity concentration in the channel layer is inversely proportional to the third power of depth into the channel layer from a top surface of the channel layer. The gate electrode has a gate length in a range from 0.2 μm to 0.6 μm.
摘要翻译：半导体器件包括：化合物半导体衬底; 顺序地设置在化合物半导体衬底上的缓冲层，沟道层和肖特基结形成层，缓冲层，沟道层和肖特基结形成层均为化合物半导体材料; 位于肖特基结形成层上的源电极和漏电极; 以及设置在源极和漏极之间并与肖特基结形成层形成肖特基结的栅电极。沟道层中的掺杂剂杂质浓度与从沟道层的顶表面进入沟道层的深度的第三功率成反比。栅电极的栅极长度在0.2μm至0.6μm的范围内。

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