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1. 发明授权

US08599968B2 Sampling circuit and receiver utilizing the same 有权
标题翻译：采样电路和接收机利用它
公开(公告)号：US08599968B2
公开(公告)日：2013-12-03
申请号：US13121244
申请日：2009-12-04
申请人： Yohei Morishita , Noriaki Saito , Yoshito Shimizu
发明人： Yohei Morishita , Noriaki Saito , Yoshito Shimizu
IPC分类号： H03D3/00
CPC分类号： H03H19/004 , H03H15/00 , H04B1/28
摘要： A sampling circuit and a receiver have a high level of filter design flexibility and excellent image rejection characteristics. Signals with phases that differ by 90° are sampled using an IQ generating circuit and are weighted by each of multiple parallel-connected discrete-time circuits, and the result of addition by an output adding circuit is ultimately output. Alternatively, a configuration in which the multiple parallel-connected discrete-time circuits and the output adding circuit are cascade-connected is adopted, so that frequency characteristics having an attenuation pole to one side can be achieved and excellent image rejection characteristics can be obtained.
摘要翻译：采样电路和接收器具有高水平的滤波器设计灵活性和出色的图像抑制特性。使用IQ产生电路对相位差90°的信号进行采样，并由多个并联连接的离散时间电路中的每一个进行加权，最后输出输出加法电路的相加结果。或者，采用并联连接的多个并联连接的离散时间电路和输出加法电路串联的结构，从而能够实现具有一侧衰减极点的频率特性，并且可以获得优异的图像抑制特性。

2. 发明申请

US20110176640A1 SAMPLING CIRCUIT AND RECEIVER UTILIZING THE SAME 有权
标题翻译：采样电路和接收器使用它
公开(公告)号：US20110176640A1
公开(公告)日：2011-07-21
申请号：US13121244
申请日：2009-12-04
申请人： Yohei Morishita , Noriaki Saito , Yoshito Shimizu
发明人： Yohei Morishita , Noriaki Saito , Yoshito Shimizu
IPC分类号： H04L25/06 , G11C27/02
CPC分类号： H03H19/004 , H03H15/00 , H04B1/28
摘要： Disclosed are a sampling circuit and a receiver that have a high level of filter design flexibility and excellent image rejection characteristics. Signals with phases that differ by 90° are sampled using an IQ generating circuit (101) and are weighted by each of multiple parallel-connected discrete-time circuits (102-1-102-n), and the result of addition by an output adding circuit (103) is ultimately output. Alternatively, a configuration in which the multiple parallel-connected discrete-time circuits (102-1-102-n) and the output adding circuit (103) are cascade-connected is adopted, so that frequency characteristics having an attenuation pole to one side can be achieved and excellent image rejection characteristics can be obtained.
摘要翻译：公开了具有高水平的滤波器设计灵活性和优异的图像抑制特性的采样电路和接收器。使用IQ生成电路（101）对具有相差90°的相位的信号进行采样，并由多个并联连接的离散时间电路（102-1-102-n）中的每一个进行加权，并且通过输出最终输出加法电路（103）。或者，采用其中并联连接的多个离散时间电路（102-1-102-n）和输出加法电路（103）串联的配置，使得具有到一侧具有衰减极点的频率特性并且可以获得优异的图像抑制特性。

3. 发明申请

US20110279164A1 MULTIPHASE MIXER 有权
标题翻译：多相混合器
公开(公告)号：US20110279164A1
公开(公告)日：2011-11-17
申请号：US13146085
申请日：2010-01-29
申请人： Yoshito Shimizu , Yohei Morishita
发明人： Yoshito Shimizu , Yohei Morishita
IPC分类号： G06G7/12
CPC分类号： H03D7/1441 , H03D7/1466 , H03D7/1483
摘要： Disclosed is a mixer able to simultaneously suppress self-mixing and low-order harmonic response in a charge sampling circuit. Specifically disclosed is a multiphase mixer provided with a transconductance amplifier (101) for converting a voltage signal into a current signal, an N number (where N is a natural number that is 2 or more) of first integrators (401, 402) which are connected in parallel to the subsequent stage of the transconductance amplifier (101), and a 2N number of mixers (102, 103, 104, 105) connected in parallel in pairs to the respective N number of first integrators (401, 402), wherein two mixers connected to the same first integrator of any of the N number of first integrators (401, 402) are controlled by driving signals comprised of pulse trains with the same frequency and phases differing by 180°.
摘要翻译：公开了能够同时抑制充电采样电路中的自混合和低次谐波响应的混频器。具体公开了一种多相混频器，其具有用于将电压信号转换为电流信号的跨导放大器（101），第一积分器（401,402）的N数（其中N为2以上的自然数）为与跨导放大器（101）的后续级并联连接，并且2N个混合器（102,103,104,105）成对并联连接到相应的N个第一积分器（401,402），其中连接到N个第一积分器（401,402）中的任一个的相同第一积分器的两个混频器由具有相同频率和相位相差180°的脉冲串组成的驱动信号来控制。

4. 发明授权

US08476952B2 Multiphase mixer 有权
标题翻译：多相混合器
公开(公告)号：US08476952B2
公开(公告)日：2013-07-02
申请号：US13146085
申请日：2010-01-29
申请人： Yoshito Shimizu , Yohei Morishita
发明人： Yoshito Shimizu , Yohei Morishita
IPC分类号： H03H11/16
CPC分类号： H03D7/1441 , H03D7/1466 , H03D7/1483
摘要： Disclosed is a mixer able to simultaneously suppress self-mixing and low-order harmonic response in a charge sampling circuit. Specifically disclosed is a multiphase mixer provided with a transconductance amplifier (101) for converting a voltage signal into a current signal, an N number (where N is a natural number that is 2 or more) of first integrators (401, 402) which are connected in parallel to the subsequent stage of the transconductance amplifier (101), and a 2N number of mixers (102, 103, 104, 105) connected in parallel in pairs to the respective N number of first integrators (401, 402), wherein two mixers connected to the same first integrator of any of the N number of first integrators (401, 402) are controlled by driving signals comprised of pulse trains with the same frequency and phases differing by 180°.
摘要翻译：公开了能够同时抑制充电采样电路中的自混合和低次谐波响应的混频器。具体公开了一种多相混频器，其具有用于将电压信号转换为电流信号的跨导放大器（101），第一积分器（401,402）的N数（其中N为2以上的自然数）为与跨导放大器（101）的后续级并联连接，并且2N个混合器（102,103,104,105）成对并联连接到相应的N个第一积分器（401,402），其中连接到N个第一积分器（401,402）中的任一个的相同第一积分器的两个混频器由具有相同频率和相位相差180°的脉冲串组成的驱动信号来控制。

5. 发明授权

US08570100B2 Direct sampling circuit and receiver 有权
标题翻译：直接采样电路和接收器
公开(公告)号：US08570100B2
公开(公告)日：2013-10-29
申请号：US13122475
申请日：2010-08-30
申请人： Yohei Morishita , Noriaki Saito
发明人： Yohei Morishita , Noriaki Saito
IPC分类号： H04B1/10 , H04B1/28
CPC分类号： H03H15/023 , H04B1/0007
摘要： A sampling circuit and a receiver, with relatively simple configurations, and clocks, exhibiting excellent frequency characteristics, are provided. In discrete time circuits, a charging switch is controlled on and off using one of four-phase control signals. A rotate capacitor shares electrical charge accumulated in an IQ generating circuit via the charging switch. A dump switch is controlled on and off using a different signal from the control signal used to control the charging switch on and off, among the four-phase control signals. A buffer capacitor shares electrical charge with the rotate capacitor via the dump switch to form an output value.
摘要翻译：提供具有相对简单的配置的采样电路和接收器以及具有优异频率特性的时钟。在离散时间电路中，使用四相控制信号之一控制充电开关的导通和截止。旋转电容器通过充电开关共享累积在IQ发生电路中的电荷。在四相控制信号中，使用与用于控制充电开关的控制信号不同的信号来控制开关的转储开关。缓冲电容器通过转储开关与旋转电容器共用电荷，形成输出值。

6. 发明申请

US20090009155A1 Discrete Time Direct Sampling Circuit and Receiver 有权
标题翻译：离散时间直接采样电路和接收机
公开(公告)号：US20090009155A1
公开(公告)日：2009-01-08
申请号：US12281668
申请日：2007-03-05
申请人： Yoshifumi Hosokawa , Katsuaki Abe , Noriaki Saito , Kiyomichi Araki , Yohei Morishita
发明人： Yoshifumi Hosokawa , Katsuaki Abe , Noriaki Saito , Kiyomichi Araki , Yohei Morishita
IPC分类号： G01R13/34 , H04B1/30
CPC分类号： H03H15/023 , H03D7/125 , H03D7/16 , H03J2200/10
摘要： A direct sampling circuit and a receiver which carry out discrete time analog processing with a high degree of design freedom and are provided with a filter property which is achievable to comply with the receipt of a broad band signal. A plurality of discrete time analog processing circuits (101) are connected in parallel with each other, a gm value and a capacitance of a capacitor in each circuit system are set independently based on a prescribed condition, and an output signal obtained from each circuit system is synthesized by means of a buffer capacitor (102), so that an equivalently high-dimensional IIR filter can be put into practice.
摘要翻译：一种直接采样电路和接收器，其以高度的设计自由度进行离散时间模拟处理，并具有能够符合宽带信号接收的滤波器特性。多个离散时间模拟处理电路（101）彼此并联连接，每个电路系统中的电容器的gm值和电容被独立地基于规定条件设置，并且从每个电路系统获得的输出信号通过缓冲电容器（102）合成，从而可以实现等效的高维IIR滤波器。

7. 发明授权

US08229987B2 Discrete time direct sampling circuit and receiver 有权
标题翻译：离散时间直接采样电路和接收器
公开(公告)号：US08229987B2
公开(公告)日：2012-07-24
申请号：US12281668
申请日：2007-03-05
申请人： Yoshifumi Hosokawa , Katsuaki Abe , Noriaki Saito , Kiyomichi Araki , Yohei Morishita
发明人： Yoshifumi Hosokawa , Katsuaki Abe , Noriaki Saito , Kiyomichi Araki , Yohei Morishita
IPC分类号： G06F17/17 , G06G7/28 , H03M1/00
CPC分类号： H03H15/023 , H03D7/125 , H03D7/16 , H03J2200/10
摘要： A direct sampling circuit and a receiver which carry out discrete time analog processing with a high degree of design freedom and are provided with a filter property which is achievable to comply with the receipt of a broad band signal. A plurality of discrete time analog processing circuits (101) are connected in parallel with each other, a gm value and a capacitance of a capacitor in each circuit system are set independently based on a prescribed condition, and an output signal obtained from each circuit system is synthesized by means of a buffer capacitor (102), so that an equivalently high-dimensional IIR filter can be put into practice.
摘要翻译：一种直接采样电路和接收器，其以高度的设计自由度进行离散时间模拟处理，并具有能够符合宽带信号接收的滤波器特性。多个离散时间模拟处理电路（101）彼此并联连接，每个电路系统中的电容器的gm值和电容被独立地基于规定条件设置，并且从每个电路系统获得的输出信号通过缓冲电容器（102）合成，从而可以实现等效的高维IIR滤波器。

8. 发明申请

US20110199122A1 DIRECT SAMPLING CIRCUIT AND RECEIVER 有权
标题翻译：直接采样电路和接收器
公开(公告)号：US20110199122A1
公开(公告)日：2011-08-18
申请号：US13122475
申请日：2010-08-30
申请人： Yohei Morishita , Noriaki Saito
发明人： Yohei Morishita , Noriaki Saito
IPC分类号： H03H19/00 , H03K3/00
CPC分类号： H03H15/023 , H04B1/0007
摘要： A sampling circuit and a receiver with relatively simple configuration and clocks, exhibiting excellent frequency characteristics, are provided. In discrete time circuits (102-1 to 102-4), charging switch (1021) is controlled on and off using one of four-phase control signals. Rotate capacitor (1022) shares electrical charge accumulated in IQ generating circuit (101) via charging switch (1021). Dump switch (1023) is controlled on and off using a different signal from the control signal used to control charging switch (1021) on and off, among the four-phase control signals. Buffer capacitor (1026) shares electrical charge with rotate capacitor (1022) via dump switch (1023) to form an output value.
摘要翻译：提供具有相对简单的配置和时钟的采样电路和接收机，具有出色的频率特性。在离散时间电路（102-1至102-4）中，使用四相控制信号之一来控制充电开关（1021）的导通和截止。旋转电容器（1022）经由充电开关（1021）共享积分在IQ发生电路（101）中的电荷。在四相控制信号中，使用与用于控制充电开关（1021）的控制信号不同的信号来开启和关闭转储开关（1023）。缓冲电容器（1026）通过转储开关（1023）与旋转电容器（1022）共享电荷以形成输出值。

9. 发明授权

US08433276B2 Sampling circuit and receiver 有权
标题翻译：采样电路和接收器
公开(公告)号：US08433276B2
公开(公告)日：2013-04-30
申请号：US13119516
申请日：2009-12-03
申请人： Yohei Morishita
发明人： Yohei Morishita
IPC分类号： H04B1/26 , G06G7/12
CPC分类号： H04B1/28 , H03H15/023
摘要： A sampling circuit and a receiver with which filter characteristics compatible with the reception of wideband signals can be realized with a high degree of freedom in the setting of the filter characteristics. More specifically, the sampling circuit is capable of removing adjacent interfering wave signals while keeping in-band deviation small. The sampling circuit is equipped with a discrete-time analog processing circuit group, wherein multiple discrete-time analog processing circuits are connected in parallel, a synthesizer that synthesizes the output signals from each of the circuit systems and outputs same, and a digital control unit that outputs control signals. Each of the discrete-time analog processing circuits is configured to include multiple rotate capacitor units, which each includes a main rotate capacitor and a sub-rotate capacitor, and only the main rotate capacitors share electric charge with a buffer capacitor included in the synthesizer.
摘要翻译：可以在滤波器特性的设定中具有高的自由度来实现与宽带信号的接收兼容的滤波特性的采样电路和接收器。更具体地，采样电路能够在保持带内偏差小的同时去除相邻的干扰波信号。采样电路配备有离散时间模拟处理电路组，其中多个离散时间模拟处理电路并联，合成器，其合成来自每个电路系统的输出信号并输出相同的数字控制单元输出控制信号。每个离散时间模拟处理电路被配置为包括多个旋转电容器单元，每个包括主旋转电容器和副旋转电容器，并且只有主旋转电容器与合成器中包括的缓冲电容器共享电荷。

10. 发明申请

US20130222164A1 DISCRETE TIME ANALOG CIRCUIT AND RECEIVER USING SAME 有权
标题翻译：离散时间模拟电路和接收器使用相同
公开(公告)号：US20130222164A1
公开(公告)日：2013-08-29
申请号：US13808481
申请日：2011-07-27
申请人： Hiroka Shiozaki , Kiyomichi Araki , Yohei Morishita , Masaki Kanemaru
发明人： Hiroka Shiozaki , Kiyomichi Araki , Yohei Morishita , Masaki Kanemaru
IPC分类号： H03M1/18 , H03M1/50
CPC分类号： H03M1/18 , H03H15/00 , H03H19/004 , H03M1/50
摘要： The discrete time analog circuit (100) is provided with: a rotate capacitor circuit (150); an amplifier (141) that is connected to the input line or the output line of the rotate capacitor (150), and amplifies the input potential or input charge; a coefficient circuit (140) that is positioned in series with the amplifier (141), and has two history capacitors (143-1, 143-2) positioned parallel to each other; a first active capacitor among the two history capacitors (143-1, 143-2) that is connected to and charges the amplifier (141); and a clock generation circuit (110) that is connected to the input line or the output line without the involvement of the amplifier (141), and that sequentially changes the pairing of the rotate capacitor circuit (150) a second active capacitor, which shares a charge with the rotate capacitor circuit (150).
摘要翻译：离散时间模拟电路（100）具有：旋转电容电路（150）; 连接到所述旋转电容器（150）的输入线或输出线的放大器（141），并放大所述输入电位或输入电荷; 与放大器（141）串联定位的系数电路（140），并且具有彼此平行定位的两个历史电容器（143-1,143-2）; 在两个历史电容器（143-1,143-2）之间连接并对放大器（141）充电的第一有源电容器; 以及时钟发生电路（110），其连接到所述输入线或所述输出线而不涉及所述放大器（141），并且顺序地改变所述旋转电容器电路（150）的配对，所述第二有源电容器与旋转电容电路（150）的电荷。

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