专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07716562B1 Reduced processing in high-speed reed-solomon decoding 有权
标题翻译：减少了高速芦苇解码中的处理
公开(公告)号：US07716562B1
公开(公告)日：2010-05-11
申请号：US11254068
申请日：2005-10-18
申请人： Yingquan Wu , Meng-Kun Lee , Kwok Alfred Yeung
发明人： Yingquan Wu , Meng-Kun Lee , Kwok Alfred Yeung
IPC分类号： H03M13/00
CPC分类号： H03M13/153 , H03M13/1515 , H03M13/1585 , H03M13/6561
摘要： Processing polynomials is disclosed. At least a portion of processing associated with an error evaluator polynomial and at least a portion of processing associated with an error locator polynomial are performed simultaneously. The error evaluator polynomial and the error locator polynomial are associated with Berlekamp-Massey processing. Data associated with the error evaluator polynomial is progressively removed.
摘要翻译：公开了处理多项式。同时执行与错误评估器多项式相关联的处理的至少一部分和与错误定位器多项式相关联的处理的至少一部分。误差评估器多项式和误差定位多项式与Berlekamp-Massey处理相关联。与错误评估器多项式相关联的数据逐渐删除。

2. 发明授权

US07903462B1 E/P durability by using a sub-range of a full programming range 有权
标题翻译：使用完整编程范围的子范围的E / P耐久性
公开(公告)号：US07903462B1
公开(公告)日：2011-03-08
申请号：US12286104
申请日：2008-09-26
申请人： Kwok Alfred Yeung , Meng-Kun Lee
发明人： Kwok Alfred Yeung , Meng-Kun Lee
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C11/5635 , G11C16/0483 , G11C16/16 , G11C16/344 , G11C16/349 , G11C2211/5621 , G11C2211/5646
摘要： A NAND flash memory system is controlled by determining whether to change a value of a voltage threshold. The voltage threshold is associated with an erase operation to a portion of a NAND flash memory chip. In the event it is determined to change the value of the voltage threshold, the value of the voltage threshold is changed and the changed value of the voltage threshold and an identifier associated with the portion of the NAND flash memory chip is stored.
摘要翻译：通过确定是否改变电压阈值的值来控制NAND快闪存储器系统。电压阈值与对NAND闪存芯片的一部分的擦除操作相关联。在确定改变电压阈值的值的情况下，改变电压阈值，并且存储电压阈值的变化值和与NAND闪速存储器芯片的部分相关联的标识符。

3. 发明授权

US07958427B1 ECC with out of order completion 有权
标题翻译： ECC无序完成
公开(公告)号：US07958427B1
公开(公告)日：2011-06-07
申请号：US11787140
申请日：2007-04-13
申请人： Kwok Alfred Yeung , Kin Ming Chan , Meng-Kun Lee
发明人： Kwok Alfred Yeung , Kin Ming Chan , Meng-Kun Lee
IPC分类号： H03M13/00
CPC分类号： H03M13/1145 , H03M13/1102 , H03M13/1515 , H03M13/153 , H03M13/1545 , H03M13/2957 , H03M13/4146 , H03M13/612
摘要： Processing a sequence of data frames in an error correction code (ECC) decoder is disclosed. Processing includes receiving a first data frame in the sequence of data frames, storing the first data frame, initiating processing of the first data frame through the ECC decoder, receiving a second data frame from the input sequence of data frames, storing the second data frame, and initiating processing of the second data frame through the ECC decoder before the first data frame is finished being processed through the ECC decoder.
摘要翻译：公开了在纠错码（ECC）解码器中处理数据帧序列。处理包括以数据帧序列接收第一数据帧，存储第一数据帧，通过ECC解码器发起第一数据帧的处理，从输入数据帧序列接收第二数据帧，存储第二数据帧，并且在通过ECC解码器处理完第一数据帧之前通过ECC解码器发起第二数据帧的处理。

4. 发明授权

US08281212B1 Iterative ECC decoder with out of order completion 有权
标题翻译：迭代ECC解码器无序完成
公开(公告)号：US08281212B1
公开(公告)日：2012-10-02
申请号：US12148777
申请日：2008-04-22
申请人： Kwok Alfred Yeung , Kin Ming Chan , Meng-Kun Lee , Kin Man Ng
发明人： Kwok Alfred Yeung , Kin Ming Chan , Meng-Kun Lee , Kin Man Ng
IPC分类号： H03M13/00
CPC分类号： H03M13/2957 , H03M13/1102 , H03M13/1145 , H03M13/1515 , H03M13/153 , H03M13/1545 , H03M13/4146 , H03M13/612
摘要： Processing a sequence of data frames in an error correction code (ECC) decoder is disclosed. Processing includes receiving a first data frame in the sequence of data frames, storing the first data frame, initiating processing of the first data frame using the ECC decoder that includes a faster stage and a slower stage, receiving a second data frame from the input sequence of data frames, storing the second data frame, and initiating processing of the second data frame through the ECC decoder before the first data frame is finished being processed using the ECC decoder.
摘要翻译：公开了在纠错码（ECC）解码器中处理数据帧序列。处理包括以数据帧序列接收第一数据帧，存储第一数据帧，使用包括更快级和较慢级的ECC解码器开始处理第一数据帧，从输入序列接收第二数据帧的数据帧，存储第二数据帧，以及在使用ECC解码器处理完第一数据帧之前通过ECC解码器发起第二数据帧的处理。

5. 发明授权

US08327241B2 Reduced processing in high-speed Reed-Solomon decoding 有权
标题翻译：在高速Reed-Solomon解码中减少处理
公开(公告)号：US08327241B2
公开(公告)日：2012-12-04
申请号：US12658597
申请日：2010-02-10
申请人： Yingquan Wu , Meng-Kun Lee , Kwok W. Yeung
发明人： Yingquan Wu , Meng-Kun Lee , Kwok W. Yeung
IPC分类号： H03M13/00
CPC分类号： H03M13/153 , H03M13/1515 , H03M13/1585 , H03M13/6561
摘要： Processing polynomials is disclosed. At least a portion of processing associated with an error evaluator polynomial and at least a portion of processing associated with an error locator polynomial are performed simultaneously. The error evaluator polynomial and the error locator polynomial are associated with Berlekamp-Massey processing. Data associated with the error evaluator polynomial is removed, including by shifting data in an array so that at least one element in the array is emptied in a shift.
摘要翻译：公开了处理多项式。同时执行与错误评估器多项式相关联的处理的至少一部分和与错误定位器多项式相关联的处理的至少一部分。误差评估器多项式和误差定位多项式与Berlekamp-Massey处理相关联。删除与错误评估器多项式相关联的数据，包括通过移位数组中的数据，使得数组中的至少一个元素在移位中清空。

6. 发明授权

US08681563B1 Flash multiple-pass write with accurate first-pass write 有权
标题翻译：闪存多遍写入，具有准确的第一遍写入
公开(公告)号：US08681563B1
公开(公告)日：2014-03-25
申请号：US13422774
申请日：2012-03-16
申请人： Meng-Kun Lee , Yingquan Wu
发明人： Meng-Kun Lee , Yingquan Wu
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C11/56 , G11C11/5628 , G11C16/04 , G11C16/0408 , G11C16/12 , G11C16/34 , G11C16/3427 , G11C29/021 , G11C29/028 , G11C2029/0411
摘要： An indication to store a data value in Flash memory is received. An accurate coarse write is performed, including by storing a first voltage level in the Flash memory and setting a configuration setting to a first setting. The first voltage level, when interpreted using the configuration setting at the first setting, corresponds to the data value. A fine write is performed, including by storing a second voltage level in the Flash memory and setting the configuration setting of the Flash memory to a second setting. The second voltage level, when interpreted using the configuration setting at the second setting, corresponds to the data value.
摘要翻译：接收到在Flash存储器中存储数据值的指示。执行精确的粗写操作，包括通过在闪存中存储第一电压电平并将配置设置设置为第一设置。当使用第一次设置的配置设置进行解释时，第一个电压电平对应于数据值。执行精细写入，包括通过在闪存中存储第二电压电平并将闪存的配置设置设置为第二设置。使用第二次设置时的配置设置进行解释时，第二个电压电平对应于数据值。

7. 发明申请

US20100199154A1 Reduced processing in high-speed Reed-Solomon decoding 有权
标题翻译：在高速Reed-Solomon解码中减少处理
公开(公告)号：US20100199154A1
公开(公告)日：2010-08-05
申请号：US12658597
申请日：2010-02-10
申请人： Yingquan Wu , Meng-Kun Lee , Kwok W. Yeung
发明人： Yingquan Wu , Meng-Kun Lee , Kwok W. Yeung
IPC分类号： H03M13/15 , G06F11/10
CPC分类号： H03M13/153 , H03M13/1515 , H03M13/1585 , H03M13/6561
摘要： Processing polynomials is disclosed. At least a portion of processing associated with an error evaluator polynomial and at least a portion of processing associated with an error locator polynomial are performed simultaneously. The error evaluator polynomial and the error locator polynomial are associated with Berlekamp-Massey processing. Data associated with the error evaluator polynomial is removed, including by shifting data in an array so that at least one element in the array is emptied in a shift.
摘要翻译：公开了处理多项式。同时执行与错误评估器多项式相关联的处理的至少一部分和与错误定位器多项式相关联的处理的至少一部分。误差评估器多项式和误差定位多项式与Berlekamp-Massey处理相关联。删除与错误评估器多项式相关联的数据，包括通过移位数组中的数据，使得数组中的至少一个元素在移位中清空。

8. 发明授权

US07231539B1 Reset circuit for resetting two clock domains 失效
标题翻译：用于复位两个时钟域的复位电路
公开(公告)号：US07231539B1
公开(公告)日：2007-06-12
申请号：US10885922
申请日：2004-07-07
申请人： Meng-Kun Lee , Peter Z. Onufryk
发明人： Meng-Kun Lee , Peter Z. Onufryk
IPC分类号： G06F1/04
CPC分类号： G06F1/12
摘要： A reset circuit for resetting two clock domains resets the two clock domains synchronously with a first clock signal in response to assertion of a system reset. It then de-asserts the resetting of a first of the clock domains in synchronization with the first clock signal, and de-asserts the resetting of a second of the clock domains in synchronization with a second clock signal so that the second clock domain is not operative until after the second clock signal is running.
摘要翻译：用于复位两个时钟域的复位电路响应于系统复位的断言，与第一时钟信号同步地复位两个时钟域。然后，它与第一时钟信号同步地断言第一时钟域的复位，并且与第二时钟信号同步地解除断言第二时钟域的复位，使得第二时钟域不是运行直到第二个时钟信号运行。

9. 发明授权

US09159422B1 Cross page management to avoid NAND physical page size limitation 有权
标题翻译：跨页面管理，以避免NAND物理页面大小的限制
公开(公告)号：US09159422B1
公开(公告)日：2015-10-13
申请号：US13445139
申请日：2012-04-12
申请人： Meng-Kun Lee , Priyanka Thakore , Derrick Preston Chu
发明人： Meng-Kun Lee , Priyanka Thakore , Derrick Preston Chu
IPC分类号： G11C29/18 , G11C16/04 , G11C16/10
CPC分类号： G11C16/04 , G06F11/1048 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/107 , G11C16/26
摘要： A method of writing data to non-volatile computer storage is disclosed. A logical page of data is received and stored in an intermediate storage. A first portion of the logical page is read from the intermediate storage and written to a first physical page in the non-volatile computer storage. A second portion of the logical page is read from the intermediate storage and written to a second physical page in the non-volatile computer storage. A method of reading data from non-volatile computer storage is disclosed. A first portion of a logical page is read from a first physical page in the non-volatile computer storage and written in an intermediate storage. A second portion of the logical page is read from a second physical page and written in the intermediate storage. The first portion and the second portion of the logical page are concatenated to form the logical page.
摘要翻译：公开了向非易失性计算机存储器写入数据的方法。数据的逻辑页被接收并存储在中间存储器中。从中间存储器读取逻辑页面的第一部分并写入非易失性计算机存储器中的第一物理页面。逻辑页面的第二部分从中间存储器读取并写入非易失性计算机存储器中的第二物理页面。公开了一种从非易失性计算机存储器读取数据的方法。从非易失性计算机存储器中的第一物理页面读取逻辑页面的第一部分并将其写入中间存储器。逻辑页面的第二部分从第二物理页面读取并写入中间存储器。逻辑页面的第一部分和第二部分被级联以形成逻辑页面。

10. 发明授权

US08413009B2 ECC with out of order completion 有权
标题翻译： ECC无序完成
公开(公告)号：US08413009B2
公开(公告)日：2013-04-02
申请号：US13087290
申请日：2011-04-14
申请人： Kwok W. Yeung , Kin Ming Chan , Meng-Kun Lee
发明人： Kwok W. Yeung , Kin Ming Chan , Meng-Kun Lee
IPC分类号： H03M13/00
CPC分类号： H03M13/1145 , H03M13/1102 , H03M13/1515 , H03M13/153 , H03M13/1545 , H03M13/2957 , H03M13/4146 , H03M13/612
摘要： Processing a sequence of data frames in an error correction code (ECC) decoder is disclosed. Processing includes receiving a first data frame in the sequence of data frames, storing the first data frame, initiating processing of the first data frame through the ECC decoder, receiving a second data frame from the input sequence of data frames, storing the second data frame, and initiating processing of the second data frame through the ECC decoder before the first data frame is finished being processed through the ECC decoder.
摘要翻译：公开了在纠错码（ECC）解码器中处理数据帧序列。处理包括以数据帧序列接收第一数据帧，存储第一数据帧，通过ECC解码器发起第一数据帧的处理，从输入数据帧序列接收第二数据帧，存储第二数据帧，并且在通过ECC解码器处理完第一数据帧之前通过ECC解码器发起第二数据帧的处理。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式