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    • 3. 发明授权
    • Shift register and gate driver with compensation control
    • 移位寄存器和栅极驱动器,具有补偿控制
    • US08970467B2
    • 2015-03-03
    • US12727287
    • 2010-03-19
    • Chien-Ting ChanWen-Chun WangHsi-Rong HanKuo-Chang Su
    • Chien-Ting ChanWen-Chun WangHsi-Rong HanKuo-Chang Su
    • G09G3/36G11C19/28
    • G11C19/28G09G3/3677G09G2310/0286
    • A shift register including a plurality of multi-stage shift register circuits is provided. The mth stage shift register circuit includes a node, a shift register unit and a control circuit. A first control signal, enabled in an mth period, is defined on the node. The shift register unit is controlled by an (m−1)th stage output signal provided by an (m−1)th stage shift register circuit and a clock signal for providing the enabled mth stage output signal in the mth period, and controlled by an (m+1)th stage second control signal provided by an (m+1)th stage shift register circuit for providing a disenabled mth stage output signal in the (m+1)th period. The control circuit, controlled by the clock signal, provides and outputs an mth stage second control signal to the (m−1)th stage shift register circuit according to the mth stage first control signal, wherein m is a natural number greater than 1.
    • 提供了包括多个多级移位寄存器电路的移位寄存器。 第m级移位寄存器电路包括一个节点,一个移位寄存器单元和一个控制电路。 节点上定义了第m个周期启用的第一个控制信号。 移位寄存器单元由第(m-1)级移位寄存器电路提供的第(m-1)级输出信号和用于在第m个周期中提供使能的第m级输出信号的时钟信号控制,并由 由第(m + 1)级移位寄存器电路提供的第(m + 1)级第二控制信号,用于在第(m + 1)个周期中提供不能使用的第m级输出信号。 由时钟信号控制的控制电路根据第m级第一控制信号向第(m-1)级移位寄存器电路提供第m级第二控制信号,其中m是大于1的自然数。
    • 4. 发明申请
    • Bidirectional Shift Register
    • 双向移位寄存器
    • US20110026665A1
    • 2011-02-03
    • US12839717
    • 2010-07-20
    • Chien-Ting ChanHsi-Rong HanWen-Chun Wang
    • Chien-Ting ChanHsi-Rong HanWen-Chun Wang
    • G11C19/00
    • G11C19/28
    • A bi-directional shift register includes N stages, wherein the mth stage among the N stages includes a node, an output end, first input circuit, second input circuit, and a shift register unit. N is a natural number greater than 1 and m is a natural number smaller than or equal to N. First control signal is measured on the node. The output end outputs an mth output signal. The first input circuit receives an m−1th output signal as a control signal and a power signal to accordingly generate an enabled first driving signal to the node in first period. The second input circuit receives an m+1th output signal as a control signal and a power signal to accordingly generate an enabled second driving signal to the node in second period. Controlled by the first control signal, the shift register unit generates an mth output signal in third period.
    • 双向移位寄存器包括N级,其中N级中的第m级包括节点,输出端,第一输入电路,第二输入电路和移位寄存器单元。 N是大于1的自然数,m是小于或等于N的自然数。在节点上测量第一控制信号。 输出端输出第m个输出信号。 第一输入电路接收作为控制信号的第m-1输出信号和功率信号,从而在第一周期中向该节点产生使能的第一驱动信号。 第二输入电路接收作为控制信号的第m + 1输出信号和功率信号,从而在第二周期中向节点产生使能的第二驱动信号。 由第一控制信号控制,移位寄存器单元在第三期间产生第m个输出信号。
    • 5. 发明申请
    • SHIFT REGISTER
    • 移位寄存器
    • US20100007598A1
    • 2010-01-14
    • US12500803
    • 2009-07-10
    • Chien-Ting ChanHsi-Rong HanWen-Chun Wang
    • Chien-Ting ChanHsi-Rong HanWen-Chun Wang
    • G09G3/36
    • G09G3/3677G11C19/28
    • A shift register includes multiple stages each generating a scan signal at an output terminal and including a level pull-up circuit, a level pull-down circuit, a driving circuit and a level controlling circuit. The level pull-up circuit makes the scan signal equal a first clock signal in response to an enabled level of a first control signal. The level pull-down circuit makes the scan signal equal a first voltage in response to an enabled level of a second control signal. The driving circuit controls the first control signal to be the enabled level and a disabled level in response to an enabled level of an input signal and the enabled level of the second control signal, respectively. The level controlling circuit controls the second control signal to be the disabled level and the enabled level in response to the enabled level and the disabled level of the input signal, respectively.
    • 移位寄存器包括多个级,每个级在输出端产生扫描信号,包括电平上拉电路,电平下拉电路,驱动电路和电平控制电路。 电平上拉电路使得扫描信号响应于第一控制信号的使能电平等于第一时钟信号。 电平下拉电路使得扫描信号响应于第二控制信号的使能电平而等于第一电压。 驱动电路分别响应于输入信号的使能电平和第二控制信号的使能电平,将第一控制信号控制为使能电平和禁用电平。 电平控制电路分别响应于输入信号的使能电平和禁用电平,将第二控制信号控制为禁用电平和使能电平。
    • 7. 发明授权
    • Shift register
    • 移位寄存器
    • US08456408B2
    • 2013-06-04
    • US12500803
    • 2009-07-10
    • Chien-Ting ChanHsi-Rong HanWen-Chun Wang
    • Chien-Ting ChanHsi-Rong HanWen-Chun Wang
    • G09G3/36
    • G09G3/3677G11C19/28
    • A shift register includes multiple stages each generating a scan signal at an output terminal and including a level pull-up circuit, a level pull-down circuit, a driving circuit and a level controlling circuit. The level pull-up circuit makes the scan signal equal a first clock signal in response to an enabled level of a first control signal. The level pull-down circuit makes the scan signal equal a first voltage in response to an enabled level of a second control signal. The driving circuit controls the first control signal to be the enabled level and a disabled level in response to an enabled level of an input signal and the enabled level of the second control signal, respectively. The level controlling circuit controls the second control signal to be the disabled level and the enabled level in response to the enabled level and the disabled level of the input signal, respectively.
    • 移位寄存器包括多个级,每个级在输出端产生扫描信号,包括电平上拉电路,电平下拉电路,驱动电路和电平控制电路。 电平上拉电路使得扫描信号响应于第一控制信号的使能电平等于第一时钟信号。 电平下拉电路使得扫描信号响应于第二控制信号的使能电平而等于第一电压。 驱动电路分别响应于输入信号的使能电平和第二控制信号的使能电平,将第一控制信号控制为使能电平和禁用电平。 电平控制电路分别响应于输入信号的使能电平和禁用电平,将第二控制信号控制为禁用电平和使能电平。
    • 8. 发明申请
    • Shift Register
    • 移位寄存器
    • US20100245300A1
    • 2010-09-30
    • US12727287
    • 2010-03-19
    • Chien-Ting ChanWen-Chun WangHsi-Rong HanKuo-Chang Su
    • Chien-Ting ChanWen-Chun WangHsi-Rong HanKuo-Chang Su
    • G06F3/038G11C19/00
    • G11C19/28G09G3/3677G09G2310/0286
    • A shift register including a plurality of multi-stage shift register circuits is provided. The mth stage shift register circuit includes a node, a shift register unit and a control circuit. A first control signal, enabled in an mth period, is defined on the node. The shift register unit is controlled by an (m−1)th stage output signal provided by an (m−1)th stage shift register circuit and a clock signal for providing the enabled mth stage output signal in the mth period, and controlled by an (m+1)th stage second control signal provided by an (m+1)th stage shift register circuit for providing a disenabled mth stage output signal in the (m+1)th period. The control circuit, controlled by the clock signal, provides and outputs an mth stage second control signal to the (m−1)th stage shift register circuit according to the mth stage first control signal, wherein m is a natural number greater than 1.
    • 提供了包括多个多级移位寄存器电路的移位寄存器。 第m级移位寄存器电路包括一个节点,一个移位寄存器单元和一个控制电路。 节点上定义了第m个周期启用的第一个控制信号。 移位寄存器单元由第(m-1)级移位寄存器电路提供的第(m-1)级输出信号和用于在第m个周期中提供使能的第m级输出信号的时钟信号控制,并由 由第(m + 1)级移位寄存器电路提供的第(m + 1)级第二控制信号,用于在第(m + 1)个周期中提供不能使用的第m级输出信号。 由时钟信号控制的控制电路根据第m级第一控制信号向第(m-1)级移位寄存器电路提供第m级第二控制信号,其中m是大于1的自然数。
    • 9. 发明申请
    • Shift Register
    • 移位寄存器
    • US20120206434A1
    • 2012-08-16
    • US13454952
    • 2012-04-24
    • Yi-Cheng TsaiWen-Chun WangHsi-Rong HanChien-Ting Chan
    • Yi-Cheng TsaiWen-Chun WangHsi-Rong HanChien-Ting Chan
    • G06F3/038
    • G09G3/3677G09G2310/0281G09G2310/0286G11C19/184G11C19/28
    • A shift register comprises many stages, and each of stages comprises a first, a second and a third level control unit and a first and a second control unit is provided. The first and the second level control unit respectively provides a first clock signal and a voltage to an output terminal. The first driving unit and the level control unit are coupled to a first node. The first driving unit turns on and turns off the first level control unit in response to an input signal, a second control signal and a first control signal of the next stage. The second driving unit turns on and turns off the second level control unit in response to the first control signal. The third level control unit provides a first voltage to the output terminal in response to the second control signal and the first control signal.
    • 移位寄存器包括许多级,并且每个级包括第一级,第二级和第三级控制单元以及第一和第二控制单元。 第一和第二电平控制单元分别向输出端提供第一时钟信号和电压。 第一驱动单元和电平控制单元耦合到第一节点。 响应于下一级的输入信号,第二控制信号和第一控制信号,第一驱动单元接通并关断第一电平控制单元。 第二驱动单元响应于第一控制信号而导通和关闭第二电平控制单元。 第三电平控制单元响应于第二控制信号和第一控制信号向输出端提供第一电压。
    • 10. 发明申请
    • Shift register with each stage controlled by a specific voltage of the next stage and the stage after thereof
    • 每个级的移位寄存器由下一级的特定电压和其后的级控制
    • US20080016139A1
    • 2008-01-17
    • US11822899
    • 2007-07-11
    • Yi-Cheng TsaiWen-Chun WangHsi-Rong HanChien-Ting Chan
    • Yi-Cheng TsaiWen-Chun WangHsi-Rong HanChien-Ting Chan
    • G06F7/44
    • G11C19/28G09G3/3674
    • A shift register has shift register units. The nth shift register unit includes first to third level control units and first and second driving units. The first and second level control units respectively provide a first clock signal and a first voltage to an output terminal. The first driving unit and the first level control unit are coupled to a first node, and a voltage on the first node is a first control signal. The first driving unit turns on and off the first level control unit in response to an input signal and second and third control signals. The second driving unit turns on and off the second level control unit in response to the first control signal. The third level control unit provides the first voltage to the output terminal in response to a front edge of the first control signal of the (n+2)th shift register unit.
    • 移位寄存器具有移位寄存器单元。 第n级移位寄存器单元包括第一至第三电平控制单元和第一和第二驱动单元。 第一和第二电平控制单元分别向输出端提供第一时钟信号和第一电压。 第一驱动单元和第一电平控制单元耦合到第一节点,并且第一节点上的电压是第一控制信号。 第一驱动单元响应于输入信号和第二和第三控制信号而打开和关闭第一电平控制单元。 第二驱动单元响应于第一控制信号而打开和关闭第二电平控制单元。 第三电平控制单元响应于第(n + 2)个第(&)移位寄存器单元的第一控制信号的前沿向输出端提供第一电压。