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1. 发明授权

US08667373B2 Frame boundary detection and synchronization system for data stream received by ethernet forward error correction layer 失效
标题翻译：通过以太网前向纠错层接收的数据流的帧边界检测和同步系统
公开(公告)号：US08667373B2
公开(公告)日：2014-03-04
申请号：US12894274
申请日：2010-09-30
申请人： Yin He , Yi Fan Lin , Yang Liu , Hao Yang
发明人： Yin He , Yi Fan Lin , Yang Liu , Hao Yang
IPC分类号： H03M13/00
CPC分类号： H04L1/0047 , H03M13/159 , H03M13/33 , H03M13/333 , H03M13/6561 , H04L7/048
摘要： The present invention discloses a frame boundary detection system and a synchronization system for a data stream received by an Ethernet Forward Error Correction layer. The frame boundary detection system includes a shifter, two descramblers, a syndrome generator and trapper. The error trapper includes a big-little endian mode controller for controlling the big-little endian conversion of the error trapper. If the error trapper operates in the big endian mode, the error trapper implements the function of the syndrome generator, operates at the same time with the syndrome generator, and performs a second FEC check, wherein when the shifter performs the FEC check by intercepting data with a length of one frame plus A bits, two start positions of the frame can be verified, where A is a positive integer less than a length of one frame. The invention can improve the frame boundary detection speed and the frame synchronization speed, and increase only a few hardware overheads.
摘要翻译：本发明公开了一种用于由以太网前向纠错层接收的数据流的帧边界检测系统和同步系统。帧边界检测系统包括移位器，两个解扰器，综合征发生器和捕捉器。误差捕获器包括一个大小端模式控制器，用于控制误差捕获器的大小端位转换。如果错误捕获器以大端模式工作，则误差捕获器实现校正子发生器的功能，同时与校正子发生器一起工作，并执行第二个FEC校验，其中当移位器通过拦截数据执行FEC检查长度为一帧加A位，可以验证帧的两个起始位置，其中A是小于一帧长度的正整数。本发明可以提高帧边界检测速度和帧同步速度，并且仅增加少量的硬件开销。

2. 发明授权

US08769368B2 Method and system for detecting the frame boundary of a data stream received in forward error correction layer in the ethernet 有权
标题翻译：用于检测以太网前向纠错层中接收的数据流的帧边界的方法和系统
公开(公告)号：US08769368B2
公开(公告)日：2014-07-01
申请号：US13391936
申请日：2010-07-29
申请人： Yin He , Yi Fan Lin , Yang Liu , Hao Yang
发明人： Yin He , Yi Fan Lin , Yang Liu , Hao Yang
IPC分类号： H04L7/04
CPC分类号： H04L7/048
摘要： The present invention discloses a method and system for detecting the frame boundary of a data stream received in Forward Error Correction layer in the Ethernet. The present invention can increase the speed of frame boundary detection and the speed of frame synchronization without adding any overheads of hardware.
摘要翻译：本发明公开了一种用于检测在以太网中的前向纠错层中接收的数据流的帧边界的方法和系统。本发明可以增加帧边界检测的速度和帧同步的速度，而不增加任何硬件开销。

3. 发明申请

US20120179950A1 Method and System for Detecting the Frame Boundary of a Data Stream Received in Forward Error Correction Layer in the Ethernet 有权
标题翻译：用于检测以太网前向纠错层中接收的数据流的帧边界的方法和系统
公开(公告)号：US20120179950A1
公开(公告)日：2012-07-12
申请号：US13391936
申请日：2010-07-29
申请人： Yin He , Yi Fan Lin , Yang Liu , Hao Yang
发明人： Yin He , Yi Fan Lin , Yang Liu , Hao Yang
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H04L7/048
摘要： The present invention discloses a method and system for detecting the frame boundary of a data stream received in Forward Error Correction layer in the Ethernet. The present invention can increase the speed of frame boundary detection and the speed of frame synchronization without adding any overheads of hardware.
摘要翻译：本发明公开了一种用于检测在以太网中的前向纠错层中接收的数据流的帧边界的方法和系统。本发明可以增加帧边界检测的速度和帧同步的速度，而不增加任何硬件开销。

4. 发明申请

US20110078545A1 Frame Boundary Detection and Synchronization System for Data Stream Received by Ethernet Forward Error Correction Layer 失效
标题翻译：通过以太网前向纠错层接收的数据流的帧边界检测和同步系统
公开(公告)号：US20110078545A1
公开(公告)日：2011-03-31
申请号：US12894274
申请日：2010-09-30
申请人： Yin He , Yi Fan Lin , Yang Liu , Hao Yang
发明人： Yin He , Yi Fan Lin , Yang Liu , Hao Yang
IPC分类号： H03M13/15 , G06F11/10
CPC分类号： H04L1/0047 , H03M13/159 , H03M13/33 , H03M13/333 , H03M13/6561 , H04L7/048
摘要： The present invention discloses a frame boundary detection system and a synchronization system for a data stream received by an Ethernet Forward Error Correction layer. The frame boundary detection system includes a shifter, two descramblers, a syndrome generator and trapper. The error trapper includes a big-little endian mode controller for controlling the big-little endian conversion of the error trapper. If the error trapper operates in the big endian mode, the error trapper implements the function of the syndrome generator, operates at the same time with the syndrome generator, and performs a second FEC check, wherein when the shifter performs the FEC check by intercepting data with a length of one frame plus A bits, two start positions of the frame can be verified, where A is a positive integer less than a length of one frame. The invention can improve the frame boundary detection speed and the frame synchronization speed, and increase only a few hardware overheads.
摘要翻译：本发明公开了一种用于由以太网前向纠错层接收的数据流的帧边界检测系统和同步系统。帧边界检测系统包括移位器，两个解扰器，综合征发生器和捕捉器。误差捕获器包括一个大小端模式控制器，用于控制误差捕获器的大小端位转换。如果错误捕获器以大端模式工作，则误差捕获器实现校正子发生器的功能，同时与校正子发生器一起工作，并执行第二个FEC校验，其中当移位器通过截取数据执行FEC检查长度为一帧加A位，可以验证帧的两个起始位置，其中A是小于一帧长度的正整数。本发明可以提高帧边界检测速度和帧同步速度，并且仅增加少量的硬件开销。

5. 发明申请

US20120159416A1 Constructing a Clock Tree for an Integrated Circuit Design 有权
标题翻译：构建集成电路设计的时钟树
公开(公告)号：US20120159416A1
公开(公告)日：2012-06-21
申请号：US13325102
申请日：2011-12-14
申请人： Guofan Jiang , Yi Fan Lin , Yang Liu , Hao Yang
发明人： Guofan Jiang , Yi Fan Lin , Yang Liu , Hao Yang
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/62
摘要： A method and apparatus for constructing a clock tree for an integrated circuit design is disclosed, the method comprising: extracting the path delays between the sequential devices in a placed netlist by performing timing analysis on the placed netlist; and constructing a clock tree for driving the sequential devices according to the path delays between the sequential devices so as to make the sum of the products of the timing delay between any two sequential devices and a clock tree branch weight of the two sequential devices minimum, wherein the clock tree branch weight of the two sequential devices is positively correlated with the number of clock tree levels from the branch point of the clock tree relative to the two sequential devices to the two sequential devices.
摘要翻译：公开了一种用于构建用于集成电路设计的时钟树的方法和装置，所述方法包括：通过对放置的网表执行定时分析来提取放置的网表中的顺序设备之间的路径延迟; 以及根据所述顺序设备之间的路径延迟构建用于驱动所述顺序设备的时钟树，以使得任何两个顺序设备之间的定时延迟的乘积和所述两个顺序设备的时钟树分支权重之和最小，其中两个顺序设备的时钟树分支权重与从时钟树分支点相对于两个顺序设备到两个顺序设备的时钟树电平的数量正相关。

6. 发明授权

US08484604B2 Constructing a clock tree for an integrated circuit design 有权
标题翻译：构建集成电路设计的时钟树
公开(公告)号：US08484604B2
公开(公告)日：2013-07-09
申请号：US13325102
申请日：2011-12-14
申请人： Guofan Jiang , Yi Fan Lin , Yang Liu , Hao Yang
发明人： Guofan Jiang , Yi Fan Lin , Yang Liu , Hao Yang
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/62
摘要： A method and apparatus for constructing a clock tree for an integrated circuit design is disclosed, the method comprising: extracting the path delays between the sequential devices in a placed netlist by performing timing analysis on the placed netlist; and constructing a clock tree for driving the sequential devices according to the path delays between the sequential devices so as to make the sum of the products of the timing delay between any two sequential devices and a clock tree branch weight of the two sequential devices minimum, wherein the clock tree branch weight of the two sequential devices is positively correlated with the number of clock tree levels from the branch point of the clock tree relative to the two sequential devices to the two sequential devices.
摘要翻译：公开了一种用于构建用于集成电路设计的时钟树的方法和装置，所述方法包括：通过对放置的网表执行定时分析来提取放置的网表中的顺序设备之间的路径延迟; 以及根据所述顺序设备之间的路径延迟构建用于驱动所述顺序设备的时钟树，以使得任何两个顺序设备之间的定时延迟的乘积和所述两个顺序设备的时钟树分支权重之和最小，其中两个顺序设备的时钟树分支权重与从时钟树分支点相对于两个顺序设备到两个顺序设备的时钟树电平的数量正相关。

7. 发明授权

US08495478B2 Frame boundary detection and decoding 有权
标题翻译：帧边界检测和解码
公开(公告)号：US08495478B2
公开(公告)日：2013-07-23
申请号：US13108081
申请日：2011-05-16
申请人： Yang Liu , Bo Fan , Yi Fan Lin , Yufei Li
发明人： Yang Liu , Bo Fan , Yi Fan Lin , Yufei Li
IPC分类号： H03M13/03
CPC分类号： H03M13/333 , H03M13/09 , H03M13/2742 , H03M13/51 , H03M13/6561 , H04L1/0046 , H04L7/048
摘要： Disclosed are a method and apparatus for detecting frame boundary for a data stream received at an Ethernet FEC layer, as well as a decoding method and system for the same. The apparatus for detecting frame boundary may comprise: a buffer for buffering data in a data stream, a length of the data in the buffer being greater than one frame; a syndrome generator for calculating a current syndrome based on a first data item, a second data item, and an intermediate calculation result of a previous syndrome, wherein the first data item is the last bit in a current candidate frame, and the second data item is a bit preceding the current candidate frame; and a comparator for using the current syndrome to check whether the bit preceding the current candidate frame is a frame boundary of an Ethernet FEC layer. The apparatus for detecting frame boundary can improve the speed of frame boundary detection.
摘要翻译：公开了一种用于检测在以太网FEC层接收的数据流的帧边界的方法和装置，以及用于其的解码方法和系统。用于检测帧边界的装置可以包括：用于缓冲数据流中的数据的缓冲器，缓冲器中的数据的长度大于一帧; 一种用于基于第一数据项，第二数据项和先前综合征的中间计算结果计算当前综合征的校正子发生器，其中第一数据项是当前候选帧中的最后位，并且第二数据项在当前候选帧之前有一点; 以及比较器，用于使用当前校正子来检查当前候选帧之前的位是否是以太网FEC层的帧边界。用于检测帧边界的装置可以提高帧边界检测的速度。

8. 发明申请

US20110296282A1 FRAME BOUNDARY DETECTION AND DECODING 有权
标题翻译：框架边界检测和解码
公开(公告)号：US20110296282A1
公开(公告)日：2011-12-01
申请号：US13108081
申请日：2011-05-16
申请人： Yang Liu , Bo Fan , Yi Fan Lin , Yufei Li
发明人： Yang Liu , Bo Fan , Yi Fan Lin , Yufei Li
IPC分类号： H03M13/15 , G06F11/10
CPC分类号： H03M13/333 , H03M13/09 , H03M13/2742 , H03M13/51 , H03M13/6561 , H04L1/0046 , H04L7/048
摘要： Disclosed are a method and apparatus for detecting frame boundary for a data stream received at an Ethernet FEC layer, as well as a decoding method and system for the same. The apparatus for detecting frame boundary may comprise: a buffer for buffering data in a data stream, a length of the data in the buffer being greater than one frame; a syndrome generator for calculating a current syndrome based on a first data item, a second data item, and an intermediate calculation result of a previous syndrome, wherein the first data item is the last bit in a current candidate frame, and the second data item is a bit preceding the current candidate frame; and a comparator for using the current syndrome to check whether the bit preceding the current candidate frame is a frame boundary of an Ethernet FEC layer. The apparatus for detecting frame boundary can improve the speed of frame boundary detection.
摘要翻译：公开了一种用于检测在以太网FEC层接收的数据流的帧边界的方法和装置，以及用于其的解码方法和系统。用于检测帧边界的装置可以包括：用于缓冲数据流中的数据的缓冲器，缓冲器中的数据的长度大于一帧; 一种用于基于第一数据项，第二数据项和先前综合征的中间计算结果计算当前综合征的校正子发生器，其中第一数据项是当前候选帧中的最后位，并且第二数据项在当前候选帧之前有一点; 以及比较器，用于使用当前校正子来检查当前候选帧之前的位是否是以太网FEC层的帧边界。用于检测帧边界的装置可以提高帧边界检测的速度。

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