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1. 发明授权

US09466696B2 FinFETs and methods for forming the same 有权
标题翻译： FinFET及其形成方法
公开(公告)号：US09466696B2
公开(公告)日：2016-10-11
申请号：US13356769
申请日：2012-01-24
申请人： Yi-Shien Mor , Hsiao-Chu Chen , Mu-Chi Chiang
发明人： Yi-Shien Mor , Hsiao-Chu Chen , Mu-Chi Chiang
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/66628 , H01L29/66545 , H01L29/66795 , H01L29/7851
摘要： A device includes a semiconductor fin, a gate dielectric on sidewalls of the semiconductor fin, a gate electrode over the gate dielectric, and isolation regions. The isolation regions include a first portion on a side of the semiconductor fin, wherein the first portion is underlying and aligned to a portion of the gate electrode. The semiconductor fin is over a first top surface of the first portion of the isolation regions. The isolation regions further include second portions on opposite sides of the portion of the gate electrode. The second top surfaces of the second portions of the isolation regions are higher than the first top surface of the isolation regions.
摘要翻译：器件包括半导体鳍片，在半导体鳍片的侧壁上的栅极电介质，栅极电介质上的栅电极和隔离区域。隔离区域包括在半导体鳍片的一侧上的第一部分，其中第一部分在下面并与栅电极的一部分对准。半导体鳍片在隔离区域的第一部分的第一顶表面之上。隔离区域还包括位于栅电极部分的相对侧上的第二部分。隔离区域的第二部分的第二顶表面高于隔离区域的第一顶表面。

2. 发明申请

US20130187206A1 FinFETs and Methods for Forming the Same 有权
标题翻译： FinFET及其形成方法
公开(公告)号：US20130187206A1
公开(公告)日：2013-07-25
申请号：US13356769
申请日：2012-01-24
申请人： Yi-Shien Mor , Hsiao-Chu Chen , Mu-Chi Chiang
发明人： Yi-Shien Mor , Hsiao-Chu Chen , Mu-Chi Chiang
IPC分类号： H01L29/78 , H01L21/76
CPC分类号： H01L29/66628 , H01L29/66545 , H01L29/66795 , H01L29/7851
摘要： A device includes a semiconductor fin, a gate dielectric on sidewalls of the semiconductor fin, a gate electrode over the gate dielectric, and isolation regions. The isolation regions include a first portion on a side of the semiconductor fin, wherein the first portion is underlying and aligned to a portion of the gate electrode. The semiconductor fin is over a first top surface of the first portion of the isolation regions. The isolation regions further include second portions on opposite sides of the portion of the gate electrode. The second top surfaces of the second portions of the isolation regions are higher than the first top surface of the isolation regions.
摘要翻译：器件包括半导体鳍片，在半导体鳍片的侧壁上的栅极电介质，栅极电介质上的栅电极和隔离区域。隔离区域包括在半导体鳍片的一侧上的第一部分，其中第一部分在下面并与栅电极的一部分对准。半导体鳍片在隔离区域的第一部分的第一顶表面之上。隔离区域还包括位于栅电极部分的相对侧上的第二部分。隔离区域的第二部分的第二顶表面高于隔离区域的第一顶表面。

3. 发明授权

US08659097B2 Control fin heights in FinFET structures 有权
标题翻译：控制FinFET结构的翅片高度
公开(公告)号：US08659097B2
公开(公告)日：2014-02-25
申请号：US13351135
申请日：2012-01-16
申请人： Yi-Shien Mor , Hsiao-Chu Chen , Mu-Chi Chiang
发明人： Yi-Shien Mor , Hsiao-Chu Chen , Mu-Chi Chiang
IPC分类号： H01L27/088 , H01L29/78
CPC分类号： H01L21/845 , H01L21/823431 , H01L27/0886 , H01L27/1211 , H01L29/66795 , H01L29/7848 , H01L29/785
摘要： A device includes a substrate, an isolation region at a top surface of the substrate, and a semiconductor fin over the isolation region. The semiconductor fin has a fin height smaller than about 400 Å, wherein the fin height is measured from a top surface of the semiconductor fin to a top surface of the isolation region.
摘要翻译：一种器件包括衬底，在衬底的顶表面处的隔离区域以及在隔离区域上的半导体鳍片。半导体翅片具有小于约400的翅片高度，其中翅片高度从半导体鳍片的顶表面到隔离区域的顶表面测量。

4. 发明申请

US20130228876A1 FinFET Design with LDD Extensions 有权
标题翻译： FinFET设计与LDD扩展
公开(公告)号：US20130228876A1
公开(公告)日：2013-09-05
申请号：US13411351
申请日：2012-03-02
申请人： Yi-Shien Mor , Hsiao-Chu Chen , Mu-Chi Chiang
发明人： Yi-Shien Mor , Hsiao-Chu Chen , Mu-Chi Chiang
IPC分类号： H01L27/088 , H01L21/76 , H01L21/20
CPC分类号： H01L29/66545 , H01L29/66795 , H01L29/7848 , H01L29/785
摘要： System and method for forming lightly doped drain (LDD) extensions. An embodiment comprises forming a gate electrode on a semiconductor fin and forming a dielectric layer over the gate electrode. The gate electrode is then etched to expose a portion of the semiconductor fin. The exposed portions of the fin comprise the LDD extensions.
摘要翻译：用于形成轻掺杂漏极（LDD）扩展的系统和方法。一个实施例包括在半导体鳍片上形成栅电极并在栅电极上形成电介质层。然后蚀刻栅电极以暴露半导体鳍片的一部分。翅片的暴露部分包括LDD延伸部。

5. 发明授权

US08865560B2 FinFET design with LDD extensions 有权
标题翻译： FinFET设计与LDD扩展
公开(公告)号：US08865560B2
公开(公告)日：2014-10-21
申请号：US13411351
申请日：2012-03-02
申请人： Yi-Shien Mor , Hsiao-Chu Chen , Mu-Chi Chiang
发明人： Yi-Shien Mor , Hsiao-Chu Chen , Mu-Chi Chiang
IPC分类号： H01L21/336
CPC分类号： H01L29/66545 , H01L29/66795 , H01L29/7848 , H01L29/785
摘要： System and method for forming lightly doped drain (LDD) extensions. An embodiment comprises forming a gate electrode on a semiconductor fin and forming a dielectric layer over the gate electrode. The gate electrode is then etched to expose a portion of the semiconductor fin. The exposed portions of the fin comprise the LDD extensions.
摘要翻译：用于形成轻掺杂漏极（LDD）扩展的系统和方法。一个实施例包括在半导体鳍片上形成栅电极并在栅电极上形成电介质层。然后蚀刻栅电极以暴露半导体鳍片的一部分。翅片的暴露部分包括LDD延伸部。

6. 发明申请

US20130181300A1 Control Fin Heights in FinFET Structures 有权
公开(公告)号：US20130181300A1
公开(公告)日：2013-07-18
申请号：US13351135
申请日：2012-01-16
申请人： Yi-Shien Mor , Hsiao-Chu Chen , Mu-Chi Chiang
发明人： Yi-Shien Mor , Hsiao-Chu Chen , Mu-Chi Chiang
IPC分类号： H01L27/088 , H01L21/8234 , H01L21/762
CPC分类号： H01L21/845 , H01L21/823431 , H01L27/0886 , H01L27/1211 , H01L29/66795 , H01L29/7848 , H01L29/785
摘要： A device includes a substrate, an isolation region at a top surface of the substrate, and a semiconductor fin over the isolation region. The semiconductor fin has a fin height smaller than about 400 Å, wherein the fin height is measured from a top surface of the semiconductor fin to a top surface of the isolation region

7. 发明申请

US20120025329A1 Spacer Shape Engineering for Void-Free Gap-Filling Process 有权
标题翻译：无间隙填充过程的间隔形状工程
公开(公告)号：US20120025329A1
公开(公告)日：2012-02-02
申请号：US13270585
申请日：2011-10-11
申请人： Ming-Yuah Wu , Yi-Shien Mor , Chih-Tang Peng , Chiung-Han Yeh , Kong-Beng Thei , Harry Chuang , Mong-Song Liang
发明人： Ming-Yuah Wu , Yi-Shien Mor , Chih-Tang Peng , Chiung-Han Yeh , Kong-Beng Thei , Harry Chuang , Mong-Song Liang
IPC分类号： H01L29/78
CPC分类号： H01L21/823481 , H01L21/823468 , H01L21/823475 , H01L29/6653 , H01L29/6656 , H01L29/7833 , H01L29/7843
摘要： A method of forming a semiconductor device includes providing a semiconductor substrate; forming a gate stack on the semiconductor substrate; forming a gate spacer adjacent to a sidewall of the gate stack; thinning the gate spacer; and forming a secondary gate spacer on a sidewall of the gate spacer after the step of thinning the gate spacer.
摘要翻译：一种形成半导体器件的方法包括提供半导体衬底; 在半导体衬底上形成栅叠层; 形成邻近所述栅叠层的侧壁的栅极间隔; 减薄栅间隔; 以及在所述栅极间隔物变薄的步骤之后，在所述栅极间隔物的侧壁上形成次级栅极间隔物。

8. 发明授权

US06521547B1 Method of repairing a low dielectric constant material layer 有权
标题翻译：修复低介电常数材料层的方法
公开(公告)号：US06521547B1
公开(公告)日：2003-02-18
申请号：US09682479
申请日：2001-09-07
申请人： Ting-Chang Chang , Po-Tsun Liu , Yi-Shien Mor
发明人： Ting-Chang Chang , Po-Tsun Liu , Yi-Shien Mor
IPC分类号： H01L2131
CPC分类号： H01L21/3105 , H01L21/31058 , H01L21/31138 , H01L21/76802
摘要： A method of repairing a low dielectric constant (low k) material layer starts with coating a photoresist layer on the low k material layer on a semiconductor wafer. After transferring a pattern of the photoresist layer to the low k material layer, an oxygen plasma ashing process is performed to remove the photoresist layer. Finally, by contacting the low k material layer with a solution of alkyl silane comprising an alkyl group and halo substituent, Si—OH bonds formed in the low k layer during the oxygen plasma ashing process are removed so as to repair damage to the low k material layer caused by the oxygen plasma ashing process, and to enhance a surface of the low k material layer to a hydrophobic surface to prevent moisture adhering to the surface of the low k material layer.
摘要翻译：修复低介电常数（低k）材料层的方法首先在半导体晶片上的低k材料层上涂覆光致抗蚀剂层。在将光致抗蚀剂层的图案转印到低k材料层之后，进行氧等离子体灰化处理以除去光致抗蚀剂层。最后，通过使低k材料层与包含烷基和卤素取代基的烷基硅烷的溶液接触，除去在氧等离子体灰化过程中在低k层中形成的Si-OH键，以修复对低k 由氧等离子体灰化过程引起的材料层，并且将低k材料层的表面增强到疏水表面以防止水分粘附到低k材料层的表面。

9. 发明授权

US08872339B2 Semiconductors structure with elements having different widths and methods of making the same 有权
标题翻译：具有不同宽度的元件的半导体结构及其制造方法
公开(公告)号：US08872339B2
公开(公告)日：2014-10-28
申请号：US13370828
申请日：2012-02-10
申请人： Chia-Chu Liu , Yi-Shien Mor , Kuei Shun Chen , Yu Lun Liu , Han-Hsun Chang , Shiao-Chian Yeh
发明人： Chia-Chu Liu , Yi-Shien Mor , Kuei Shun Chen , Yu Lun Liu , Han-Hsun Chang , Shiao-Chian Yeh
IPC分类号： H01L23/482 , H01L23/485 , H01L21/02
CPC分类号： H01L21/76879 , H01L21/32139 , H01L21/76802 , H01L21/76885 , H01L27/0629 , H01L2924/0002
摘要： A structure includes a substrate, a first supporting member over the substrate, a second supporting member over the substrate, and a layer of material over the substrate and covering the first supporting member and the second supporting member. The first supporting member has a first width, and the second supporting member has a second width. The first supporting member and the second supporting member are separated by a gap region. The first width is at least 10 times the second width, and a gap width of the gap region ranges from 5 to 30 times the second width.
摘要翻译：一种结构包括基底，在基底上方的第一支撑构件，在基底上方的第二支撑构件，以及在基底上方的覆盖第一支撑构件和第二支撑构件的材料层。第一支撑构件具有第一宽度，并且第二支撑构件具有第二宽度。第一支撑构件和第二支撑构件由间隙区域分开。第一宽度为第二宽度的至少10倍，间隙区域的间隙宽度为第二宽度的5至30倍。

10. 发明申请

US20100048013A1 NOVEL HIGH-K METAL GATE CMOS PATTERNING METHOD 有权
标题翻译：新型高K金属栅CMOS图案方法
公开(公告)号：US20100048013A1
公开(公告)日：2010-02-25
申请号：US12536629
申请日：2009-08-06
申请人： Kong-Beng Thei , Harry Chuang , Ryan Chia-Jen Chen , Su-Chen Lai , Yi-Shien Mor , Yi-Hsing Chen , Gary Shen , Y. C. Lin
发明人： Kong-Beng Thei , Harry Chuang , Ryan Chia-Jen Chen , Su-Chen Lai , Yi-Shien Mor , Yi-Hsing Chen , Gary Shen , Y. C. Lin
IPC分类号： H01L21/28
CPC分类号： H01L21/31645 , H01L21/31604 , H01L21/823842
摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first active region and a second active region, forming a high-k dielectric layer over the semiconductor substrate, forming a capping layer over the high-k dielectric layer, forming a first metal layer over the capping layer, the first metal layer having a first work function, forming a mask layer over the first metal layer in the first active region, removing the first metal layer and at least a portion of the capping layer in the second active region using the mask layer, and forming a second metal layer over the partially removed capping layer in the second active region, the second metal layer having a second work function.
摘要翻译：本公开提供了制造半导体器件的方法。该方法包括提供具有第一有源区和第二有源区的半导体衬底，在半导体衬底上形成高k电介质层，在高k电介质层上形成覆盖层，在覆盖层上形成第一金属层第一金属层具有第一功函数，在第一有源区中的第一金属层上形成掩模层，使用掩模层去除第一金属层和第二有源区中的覆盖层的至少一部分并且在所述第二有源区域中的所述部分去除的覆盖层上形成第二金属层，所述第二金属层具有第二功函数。

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