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1. 发明授权

US06303467B1 Method for manufacturing trench isolation 失效
标题翻译：沟槽隔离方法
公开(公告)号：US06303467B1
公开(公告)日：2001-10-16
申请号：US09628675
申请日：2000-07-28
申请人： Yi-Min Jen , Tse-Yi Lu , Ya-Ling Hung , Li-Wu Tsao
发明人： Yi-Min Jen , Tse-Yi Lu , Ya-Ling Hung , Li-Wu Tsao
IPC分类号： H01L2176
CPC分类号： H01L21/76224
摘要： A method for manufacturing trench isolation, comprising firstly, defining a trench isolation over the substrate by photolithography and etching technique. Beside, by way of a spacer fabricating process to form a spacer around each of the two sides of the trench isolation. Therefore, a sharp corner in the crossing region between the trench isolation and an active area adjacent thereto in the substrate is smoothed, and the process window for a sequential gate polysilicon etching is improved, as well as the opportunity to leave polysilicon residue in the corner is eliminated. The short circuit between polysilicon gates is also avoided.
摘要翻译：一种用于制造沟槽隔离的方法，首先，通过光刻和蚀刻技术在衬底上限定沟槽隔离。此外，通过间隔件制造工艺，在沟槽隔离的两侧的每一侧上形成间隔件。因此，在沟槽隔离和与衬底之间相邻的有源区域之间的交叉区域中的尖角被平滑化，并且用于顺序栅极多晶硅蚀刻的处理窗口以及在多个晶圆中留下多晶硅残留物的机会被淘汰。也避免了多晶硅栅之间的短路。

2. 发明授权

US06287909B1 Method of fabricating a static random access memory 有权
标题翻译：制造静态随机存取存储器的方法
公开(公告)号：US06287909B1
公开(公告)日：2001-09-11
申请号：US09578227
申请日：2000-05-24
申请人： Yi-Min Jen , Tse-Yi Lu , Yu-Chih Chuang
发明人： Yi-Min Jen , Tse-Yi Lu , Yu-Chih Chuang
IPC分类号： H01L218234
CPC分类号： H01L27/11
摘要： A method of fabricating a buried contact in a static random access memory. A gate oxide layer, a first conducting layer and a masking layer are formed sequentially on a substrate. A buried contact opening is formed inside the gate oxide layer, the first conducting layer and the masking layer, which opening exposes a part of the substrate. An epitaxial layer is formed inside the buried contact opening, which epitaxial layer fills up the buried contact opening. After the masking layer is removed, a second conducting layer is formed above the substrate. A buried contact is formed in the substrate that is below the epitaxial layer. The gate oxide layer, the first conducting layer, the epitaxial layer and second conducting layer are patterned to expose a part of the substrate and a part of the buried contact. A source/drain is formed in the substrate and a part of the source/drain is mixed with a part of the buried contact.
摘要翻译：一种在静态随机存取存储器中制造掩埋触点的方法。栅极氧化层，第一导电层和掩模层依次形成在基板上。掩模接触开口形成在栅极氧化物层内，第一导电层和掩蔽层中，该开口露出基板的一部分。在埋入接触开口内形成外延层，该外延层填充埋入的接触开口。在去除掩模层之后，在衬底上方形成第二导电层。在衬底中形成在外延层下面的掩埋接触。图案化栅极氧化物层，第一导电层，外延层和第二导电层，以暴露衬底的一部分和埋入触点的一部分。源极/漏极形成在衬底中，并且源极/漏极的一部分与埋入触点的一部分混合。

3. 发明授权

US06171951B2 Dual damascene method comprising ion implanting to densify dielectric layer and forming a hard mask layer with a tapered opening 失效
标题翻译：双镶嵌方法包括离子注入以致密化介电层并形成具有锥形开口的硬掩模层
公开(公告)号：US06171951B2
公开(公告)日：2001-01-09
申请号：US09183530
申请日：1998-10-30
申请人： Tzung-Han Lee , Tse-Yi Lu
发明人： Tzung-Han Lee , Tse-Yi Lu
IPC分类号： H01L214763
CPC分类号： H01L21/76825 , H01L21/02107 , H01L21/02203 , H01L21/02304 , H01L21/02321 , H01L21/0234 , H01L21/02351 , H01L21/02362 , H01L21/31155 , H01L21/314 , H01L21/31695 , H01L21/76801 , H01L21/7681 , H01L21/76814 , H01L21/76826 , H01L21/76831
摘要： A dual damascene manufacturing method includes utilizing a low dielectric constant material to form the dielectric layers and to prevent current due to the reduced line width. An implanting step is performed on the dielectric layers to reduce the incoherence and fragility of the dielectric layers, to densify the dielectric layers and to protect the dielectric layers from damage in the subsequent processes. The present invention utilizes the hard mask layer formed over the dielectric layer to reduce the difficulty of the depositing process of the barrier layer. The openings formed within the hard mask layer are broad at the top and narrow at the bottom. so that the barrier layer is more easily deposited into the opening and the subsequent deposition step of the conductive material layer is easily performed. Moreover, the hard mask layer can be utilized as the etching stop layer in the CMP process.
摘要翻译：双镶嵌制造方法包括利用低介电常数材料形成电介质层并且由于线宽减小而防止电流。在电介质层上执行注入步骤以减少电介质层的不相干性和脆弱性，使介电层致密化并保护介电层免于后续工艺中的损坏。本发明利用形成在电介质层上的硬掩模层来减少阻挡层的沉积过程的难度。在硬掩模层中形成的开口在顶部是宽的，在底部是窄的。使得阻挡层更容易沉积到开口中，并且容易执行导电材料层的随后的沉积步骤。此外，在CMP工艺中可以使用硬掩模层作为蚀刻停止层。

4. 发明授权

US06197629B1 Method of fabricating a polysilicon-based load circuit for static random-access memory 有权
标题翻译：制造用于静态随机存取存储器的基于多晶硅的负载电路的方法
公开(公告)号：US06197629B1
公开(公告)日：2001-03-06
申请号：US09195923
申请日：1998-11-19
申请人： Tse-Yi Lu
发明人： Tse-Yi Lu
IPC分类号： H01L218234
CPC分类号： H01L27/11 , H01L27/1112 , H01L28/20
摘要： A semiconductor fabrication method is provided for the fabrication of a polysilicon-based load circuit (called poly-load) for SRAM (static random-access memory). In accordance with this method, a lightly doped polysilicon layer is formed. This lightly doped polysilicon layer is doped with an impurity element to a predetermined concentration corresponding to the desired resistive characteristic of the poly-load. Further, this lightly-doped polysilicon layer is partitioned into two parts: a first part to be formed into the desired poly-load and a second part to be formed into a conductive interconnecting line that is electrically connected to the poly-load. After this, a metal silicide layer is formed over the second part of the lightly doped polysilicon layer to serve as the conductive interconnecting line. Next, an ILD (Inter Layer Dielectric) layer is formed over the poly-load and the conductive interconnecting line, and then the ILD layer is subjected to a densification process. This method can help the poly-load retain its specified length, thus allowing the SRAM device to be further reduced in size to a deep submicron level of integration. Moreover, the method can help the conductive interconnecting line have a low sheet resistance, thus reducing the IR drop across each memory cell to allow a SRAM device to be more stable in operation.
摘要翻译：提供半导体制造方法用于制造用于SRAM（静态随机存取存储器）的基于多晶硅的负载电路（称为多重负载）。根据该方法，形成轻掺杂多晶硅层。该轻掺杂多晶硅层掺杂有与多负载的期望电阻特性对应的预定浓度的杂质元素。此外，将这种轻掺杂多晶硅层分成两部分：要形成所需多负载的第一部分和要形成导电互连线的第二部分，导电互连线电连接到多负载。此后，在轻掺杂多晶硅层的第二部分上形成金属硅化物层以用作导电互连线。接下来，在多负载和导电互连线上形成ILD（层间电介质）层，然后对ILD层进行致密化处理。该方法可以帮助多负载保持其指定的长度，从而允许SRAM器件的尺寸进一步减小到深亚微米级的集成度。此外，该方法可以帮助导电互连线具有低的薄层电阻，从而减少每个存储单元上的IR降，使得SRAM器件在操作中更稳定。

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