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1. 发明授权

US07148934B2 Easy-maintain rear projection television 失效
标题翻译：易于维护的背投电视
公开(公告)号：US07148934B2
公开(公告)日：2006-12-12
申请号：US10707801
申请日：2004-01-13
申请人： Yi-Cheng Yuan , Chun-Yao Chen , Yung-Chuan Tseng , Chih-Chung Kang
发明人： Yi-Cheng Yuan , Chun-Yao Chen , Yung-Chuan Tseng , Chih-Chung Kang
IPC分类号： H04N5/64
CPC分类号： H04N9/3141
摘要： A rear projection television includes a casing with a space therein and a plurality of modular units. A plurality of maintenance holes are formed through the casing to communicate with the space. The modular units are positioned in the space to correspond to the maintenance holes. When one component inside the casing needs repairing, only a lid covering the corresponding maintenance hole is dismounted for the user to quickly take the component out, without moving the casing. Thereby, the repair process is simplified with saved repair labor and space.
摘要翻译：背投电视包括其中具有空间的壳体和多个模块单元。通过壳体形成多个维护孔，以与该空间连通。模块化单元位于空间中以对应于维护孔。当壳体内部的一个部件需要修理时，仅拆卸覆盖相应的维护孔的盖子，以使用户不用移动外壳即可快速取出部件。因此，修复过程简化，节省了维修人员和空间。

2. 发明授权

US06773115B2 Adjusting apparatus for projection 失效
公开(公告)号：US06773115B2
公开(公告)日：2004-08-10
申请号：US10731138
申请日：2003-12-10
申请人： Yung-Chuan Tseng , Chun-Yao Chen , Kuan-Chou Ko
发明人： Yung-Chuan Tseng , Chun-Yao Chen , Kuan-Chou Ko
IPC分类号： G03B2128
CPC分类号： G03B21/10 , G03B21/28
摘要： An adjusting apparatus for projection comprises a carrier having a central screw hole and three rounded indentations around central screw hole, an adjusting frame having a plane section and a base section, and a holder. The center of the plane section has a circular concave dug a hole with a smaller aperture. A ball bearing is accommodated in the circular concave. The plane section of the adjusting frame has three screw holes corresponding to the rounded indentations. Three angle-adjusting bolts respectively insert through the screw holes to abut against the rounded indentations. Rotating the angle-adjusting bolts relative to each other varies the length of the angle-adjusting bolts calculated from the plane section of the adjusting frame to the carrier. Thereby, an angle adjustment of a mirror is achieved.

3. 外观设计

USD483727S1 Rear projection television 失效
标题翻译：背投电视
公开(公告)号：USD483727S1
公开(公告)日：2003-12-16
申请号：US29178638
申请日：2003-03-31
申请人： Yung-Chuan Tseng , Yi-Chen Yuan , Chich-Chung Kang , Chun-Yao Chen
设计人： Yung-Chuan Tseng , Yi-Chen Yuan , Chich-Chung Kang , Chun-Yao Chen

4. 发明申请

US20070200162A1 Reducing dielectric constant for MIM capacitor 有权
标题翻译：降低MIM电容的介电常数
公开(公告)号：US20070200162A1
公开(公告)日：2007-08-30
申请号：US11361330
申请日：2006-02-24
申请人： Kuo-Chi Tu , Chun-Yao Chen , Yi-Ching Lin
发明人： Kuo-Chi Tu , Chun-Yao Chen , Yi-Ching Lin
IPC分类号： H01L29/76
CPC分类号： H01L28/40 , H01L27/10852 , H01L27/10894 , H01L28/56
摘要： A memory device having improved sensing speed and reliability and a method of forming the same are provided. The memory device includes a first dielectric layer having a low k value over a semiconductor substrate, a second dielectric layer having a second k value over the first dielectric layer, and a capacitor formed in the second dielectric layer wherein the capacitor comprises a cup region at least partially filled by the third dielectric layer. The memory device further includes a third dielectric layer over the second dielectric layer and a bitline over the third dielectric layer. The bitline is electrically coupled to the capacitor. A void having great dimensions is preferably formed in the cup region of the capacitor.
摘要翻译：提供了具有改进的感测速度和可靠性的记忆装置及其形成方法。存储器件包括在半导体衬底上具有低k值的第一电介质层，在第一介电层上具有第二k值的第二电介质层和形成在第二电介质层中的电容器，其中电容器包括位于最少部分地被第三介电层填充。存储器件还包括第二电介质层上的第三电介质层和第三电介质层上的位线。位线电耦合到电容器。优选地，在电容器的杯区域中形成具有大尺寸的空隙。

5. 发明申请

US20050280981A1 Modularized rotatable signal control box 审中-公开
标题翻译：模块化可旋转信号控制箱
公开(公告)号：US20050280981A1
公开(公告)日：2005-12-22
申请号：US11154753
申请日：2005-06-16
申请人： Chun-Yao Chen
发明人： Chun-Yao Chen
IPC分类号： G06F1/16 , H04N5/64 , H04N5/74
CPC分类号： H04N9/3141 , H04N5/64
摘要： The invention provides a modularized rotatable signal control box which is assembled in a housing of an electronic appliance. The signal control box comprises a module base and a rotatable module. The module base is assembled in the housing of the electronic appliance. The rotatable module comprises a hidden panel and at least one rotating element. The hidden panel comprises at least one signal input/output connector, and the rotating element is used for rotatably connecting the rotatable module to the module base.
摘要翻译：本发明提供一种组装在电子设备的壳体中的模块化的可旋转信号控制箱。信号控制箱包括模块基座和可旋转模块。模块底座组装在电子设备的外壳中。可旋转模块包括隐藏的面板和至少一个旋转元件。隐藏的面板包括至少一个信号输入/输出连接器，并且旋转元件用于将可旋转模块可旋转地连接到模块基座。

6. 发明授权

US6136643A Method for fabricating capacitor-over-bit-line dynamic random access memory (DRAM) using self-aligned contact etching technology 有权
标题翻译：使用自对准接触蚀刻技术制造电容器 - 位线动态随机存取存储器（DRAM）的方法
公开(公告)号：US6136643A
公开(公告)日：2000-10-24
申请号：US248727
申请日：1999-02-11
申请人： Erik S. Jeng , Chun-Yao Chen , Ing-Ruey Liaw , Janmye Sung
发明人： Erik S. Jeng , Chun-Yao Chen , Ing-Ruey Liaw , Janmye Sung
IPC分类号： H01L21/02 , H01L21/8242
CPC分类号： H01L27/10888 , H01L28/91
摘要： A method for making capacitor-over-bit line (COB) DRAM using a self-aligned contact etching technology is achieved. After forming FET gate electrodes, sidewall spacers are formed from a first Si.sub.3 N.sub.4 etch-stop layer, while a portion of the Si.sub.3 N.sub.4 is retained as an etch-stop layer on the source/drain areas. Self-aligned contact openings are etched in a first oxide layer to the source/drain areas, and polysilicon landing plugs are formed in all the self-aligned openings. A second oxide layer is deposited and contact holes are etched to the landing plugs for bit lines. A polycide layer having a cap layer is deposited and patterned to form bit lines. A third Si.sub.3 N.sub.4 etch-stop layer is conformally deposited over the bit lines and patterned to form openings over the landing plugs for the capacitor node contacts while forming Si.sub.3 N.sub.4 sidewall spacers on the bit lines exposed in the openings. A third oxide layer is deposited, and openings having relaxed alignment tolerances, can be etched to the capacitor node contacts because the underlying third etch-stop layer prevents overetching. A conducting layer is deposited and etched back to form bottom electrodes in the openings, and the third oxide layer is removed, while the Si.sub.3 N.sub.4 etch-stop layers prevents over-etching. An interelectrode dielectric layer is deposited, and capacitor top electrodes are formed.
摘要翻译：实现了使用自对准接触蚀刻技术制造电容器对位线（COB）DRAM的方法。在形成FET栅电极之后，侧壁间隔物由第一Si 3 N 4蚀刻停止层形成，而一部分Si 3 N 4作为蚀刻停止层保留在源/漏区上。自对准的接触开口在第一氧化物层中蚀刻到源极/漏极区域，并且在所有自对准开口中形成多晶硅着色塞。沉积第二氧化物层，并将接触孔蚀刻到位线的着陆塞。沉积具有盖层的多晶硅化物层并构图以形成位线。第三个Si 3 N 4蚀刻停止层被保形地沉积在位线上并被图案化以在用于电容器节点接触的着陆塞上形成开口，同时在开口中暴露的位线上形成Si 3 N 4侧壁间隔物。沉积第三氧化物层，并且具有松弛的取向公差的开口可被蚀刻到电容器节点接点，因为下面的第三蚀刻停止层防止过蚀刻。导电层被沉积并回蚀刻以在开口中形成底部电极，并且去除第三氧化物层，而Si 3 N 4蚀刻停止层防止过蚀刻。沉积电极间电介质层，形成电容器顶部电极。

7. 发明授权

US08242551B2 Metal-insulator-metal structure for system-on-chip technology 有权
标题翻译：金属 - 绝缘体 - 金属结构的片上系统技术
公开(公告)号：US08242551B2
公开(公告)日：2012-08-14
申请号：US12397948
申请日：2009-03-04
申请人： Kuo-Cheng Ching , Kuo-Chi Tu , Chun-Yao Chen
发明人： Kuo-Cheng Ching , Kuo-Chi Tu , Chun-Yao Chen
IPC分类号： H01G4/40 , H01G17/00
CPC分类号： H01L27/0805 , H01L27/0629 , H01L27/10852 , H01L27/10894 , H01L28/91
摘要： The present disclosure provides a semiconductor device that includes a semiconductor substrate, an isolation structure formed in the semiconductor substrate, a conductive layer formed over the isolation structure, and a metal-insulator-metal (MIM) capacitor formed over the isolation structure. The MIM capacitor has a crown shape that includes a top electrode, a first bottom electrode, and a dielectric disposed between the top electrode and the first bottom electrode, the first bottom electrode extending at least to a top surface of the conductive layer.
摘要翻译：本公开提供了一种半导体器件，其包括半导体衬底，形成在半导体衬底中的隔离结构，在隔离结构上形成的导电层，以及形成在隔离结构上的金属 - 绝缘体 - 金属（MIM）电容器。 MIM电容器具有冠状形状，其包括顶部电极，第一底部电极和设置在顶部电极和第一底部电极之间的电介质，第一底部电极至少延伸到导电层的顶表面。

8. 发明授权

US08215797B2 Input/output device for display apparatus 有权
标题翻译：显示装置的输入/输出装置
公开(公告)号：US08215797B2
公开(公告)日：2012-07-10
申请号：US11513201
申请日：2006-08-31
申请人： Chun-Yao Chen , Kuo-Chou Chang , Wei-Cheng Huang
发明人： Chun-Yao Chen , Kuo-Chou Chang , Wei-Cheng Huang
IPC分类号： F21V33/00 , H05K5/00
CPC分类号： H05K5/0247
摘要： An input/output device used for connecting at least one external wire with a display apparatus, comprises a case, at least one I/O connector, a flip cover, and a lighting device. The case embedded in the case of the display apparatus has a wiring slot to provide the wire passing through the case. The I/O connectors embedded on the case are electrically connected to the display apparatus. The flip cover is pivoted on the case. The lighting device having a light source and a switch is associated with the flip cover to turn on or turn off the light source.
摘要翻译：用于将至少一个外部电线与显示装置连接的输入/输出装置包括壳体，至少一个I / O连接器，翻盖和照明装置。在显示装置的情况下嵌入的壳体具有配线槽，用于提供穿过壳体的电线。嵌入在壳体上的I / O连接器电连接到显示装置。翻盖在壳体上枢转。具有光源和开关的照明装置与翻盖相关联以打开或关闭光源。

9. 发明授权

US07382012B2 Reducing parasitic capacitance of MIM capacitor in integrated circuits by reducing effective dielectric constant of dielectric layer 有权
标题翻译：通过降低介电层的有效介电常数，降低集成电路中MIM电容的寄生电容
公开(公告)号：US07382012B2
公开(公告)日：2008-06-03
申请号：US11361330
申请日：2006-02-24
申请人： Kuo-Chi Tu , Chun-Yao Chen , Yi-Ching Lin
发明人： Kuo-Chi Tu , Chun-Yao Chen , Yi-Ching Lin
IPC分类号： H01L27/108 , H01L21/20 , G11C11/00
CPC分类号： H01L28/40 , H01L27/10852 , H01L27/10894 , H01L28/56
摘要： A memory device having improved sensing speed and reliability and a method of forming the same are provided. The memory device includes a first dielectric layer having a low k value over a semiconductor substrate, a second dielectric layer having a second k value over the first dielectric layer, and a capacitor formed in the second dielectric layer wherein the capacitor comprises a cup region at least partially filled by the third dielectric layer. The memory device further includes a third dielectric layer over the second dielectric layer and a bitline over the third dielectric layer. The bitline is electrically coupled to the capacitor. A void having great dimensions is preferably formed in the cup region of the capacitor.
摘要翻译：提供了具有改进的感测速度和可靠性的记忆装置及其形成方法。存储器件包括在半导体衬底上具有低k值的第一电介质层，在第一介电层上具有第二k值的第二电介质层和形成在第二电介质层中的电容器，其中电容器包括位于最少部分地被第三介电层填充。存储器件还包括第二电介质层上的第三电介质层和第三电介质层上的位线。位线电耦合到电容器。优选地，在电容器的杯区域中形成具有大尺寸的空隙。

10. 发明申请

US20080122032A1 Semiconductor devices with MIM-type decoupling capacitors and fabrication method thereof 审中-公开
标题翻译：具有MIM型去耦电容器的半导体器件及其制造方法
公开(公告)号：US20080122032A1
公开(公告)日：2008-05-29
申请号：US11504693
申请日：2006-08-16
申请人： Kuo-Chi Tu , Chun-Yao Chen
发明人： Kuo-Chi Tu , Chun-Yao Chen
IPC分类号： H01L29/00 , H01L21/02
CPC分类号： H01L28/91 , H01L28/55
摘要： A semiconductor device. The semiconductor device includes a substrate having an array region and a decoupling region, a first dielectric layer overlying the substrate, a second dielectric layer overlying the first dielectric layer, a plurality of active components formed in the first dielectric layer within the array region, a first capacitor formed in the second dielectric layer within the array region, a second capacitor formed in the second dielectric layer within the decoupling region, and a first plug formed in the first dielectric layer within the array region electrically connecting the active component and the first capacitor. The invention also provides a method of fabricating the semiconductor device.
摘要翻译：半导体器件。半导体器件包括具有阵列区和去耦区的衬底，覆盖衬底的第一电介质层，覆盖第一电介质层的第二电介质层，形成在阵列区域内的第一电介质层中的多个有源元件，形成在阵列区域内的第二电介质层中的第一电容器，形成在去耦区域内的第二电介质层中的第二电容器和形成在阵列区域内的第一电介质层中的电连接有源部件和第一电容器。本发明还提供一种制造半导体器件的方法。

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