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1. 发明申请

US20130219347A1 METHODS FOR DECOMPOSING CIRCUIT DESIGN LAYOUTS AND FOR FABRICATING SEMICONDUCTOR DEVICES USING DECOMPOSED PATTERNS 有权
标题翻译：用于分解电路设计层和使用分解图案制作半导体器件的方法
公开(公告)号：US20130219347A1
公开(公告)日：2013-08-22
申请号：US13400445
申请日：2012-02-20
申请人： Yi Zou , Swamy Muddu , Lynn T. Wang , Vito Dai , Luigi Capodieci , Peng Xie
发明人： Yi Zou , Swamy Muddu , Lynn T. Wang , Vito Dai , Luigi Capodieci , Peng Xie
IPC分类号： G06F17/50
CPC分类号： G03F1/70
摘要： Methods for fabricating semiconductor devices are provided. In an embodiment, a method of fabricating a semiconductor device includes scanning a circuit design layout and proposing patterns for decomposed layouts. The proposed patterns are then compared with a library of prior patterns including a category of forbidden patterns and a category of preferred patterns. If a selected proposed pattern matches a forbidden pattern, the selected proposed pattern is eliminated. If the selected proposed pattern matches a preferred pattern, then the selected proposed pattern is identified for use in the decomposed layouts. Decomposed layouts are generated from the identified patterns. A plurality of masks is fabricated based on the decomposed layouts. Then a multiple patterning lithographic technique is performed with the plurality of masks on a semiconductor substrate.
摘要翻译：提供制造半导体器件的方法。在一个实施例中，制造半导体器件的方法包括扫描电路设计布局并提出用于分解布局的图案。然后将所提出的模式与包括禁止模式类别和优选模式类别的先前模式的库进行比较。如果所选择的提议模式匹配禁止模式，则删除所选择的提议模式。如果所选择的提出的模式匹配优选模式，则所选择的提出的模式被识别用于分解的布局。分辨的布局是从识别的图案生成的。基于分解的布局制造多个掩模。然后用半导体衬底上的多个掩模进行多重图形化光刻技术。

2. 发明申请

US20130212548A1 METHODS FOR ANALYZING DESIGN RULES 有权
标题翻译：分析设计规则的方法
公开(公告)号：US20130212548A1
公开(公告)日：2013-08-15
申请号：US13369938
申请日：2012-02-09
申请人： Swamy Muddu , Abde Ali Kagalwalla , Luigi Capodieci
发明人： Swamy Muddu , Abde Ali Kagalwalla , Luigi Capodieci
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： Methods and apparatus are provided for analyzing impact of design rules on a layout. One exemplary method involves generating variants of the layout for different values for the rule, determining values of a device metric for each of the layout variants, and identifying the relationship between rule and the device metric based on the values for the device metric corresponding to the different values for the rule. In one embodiment, the layout variants are generated by using the different values for the rule to perform layout compaction on an initial layout generated in accordance with an initial value for the rule.
摘要翻译：提供了方法和设备，用于分析设计规则对布局的影响。一个示例性方法涉及为规则的不同值生成布局的变体，确定每个布局变体的设备度量的值，以及基于对应于设备度量的设备度量的值来识别规则与设备度量之间的关系规则的不同值。在一个实施例中，通过使用规则的不同值来根据规则的初始值生成的初始布局来执行布局压缩来生成布局变体。

3. 发明授权

US08589844B2 Methods for analyzing design rules 有权
标题翻译：分析设计规则的方法
公开(公告)号：US08589844B2
公开(公告)日：2013-11-19
申请号：US13369938
申请日：2012-02-09
申请人： Swamy Muddu , Abde Ali Kagalwalla , Luigi Capodieci
发明人： Swamy Muddu , Abde Ali Kagalwalla , Luigi Capodieci
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5081
摘要： Methods and apparatus are provided for analyzing impact of design rules on a layout. One exemplary method involves generating variants of the layout for different values for the rule, determining values of a device metric for each of the layout variants, and identifying the relationship between rule and the device metric based on the values for the device metric corresponding to the different values for the rule. In one embodiment, the layout variants are generated by using the different values for the rule to perform layout compaction on an initial layout generated in accordance with an initial value for the rule.
摘要翻译：提供了方法和设备，用于分析设计规则对布局的影响。一个示例性方法涉及为规则的不同值生成布局的变体，确定每个布局变体的设备度量的值，以及基于对应于设备度量的设备度量的值来识别规则与设备度量之间的关系规则的不同值。在一个实施例中，通过使用规则的不同值来根据规则的初始值生成的初始布局来执行布局压缩来生成布局变体。

4. 发明授权

US08024675B1 Method and system for wafer topography-aware integrated circuit design analysis and optimization 有权
标题翻译：晶圆地形识别集成电路设计分析与优化方法与系统
公开(公告)号：US08024675B1
公开(公告)日：2011-09-20
申请号：US11499070
申请日：2006-08-04
申请人： Puneet Gupta , Andrew Kahng , Puneet Sharma , Swamy Muddu
发明人： Puneet Gupta , Andrew Kahng , Puneet Sharma , Swamy Muddu
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： A method and system for designing an optimized specification of an integrated circuit (IC) is provided. The IC comprises a plurality of cells, and each of the cells comprises a plurality of transistors. The method includes preparing a linewidth map of at least one device of the plurality of devices, performing a topography-aware analysis of the at least one device based on the linewidth map, and designing the optimized specification of the IC based on the topography-aware analysis. In another embodiment, a method for estimating a leakage power of at least one device in an IC is provided. The method includes determining a defocus and a pitch value, determining a linewidth value based on the defocus and pitch value, and estimating the leakage current and/or leakage power based on the linewidth value.
摘要翻译：提供了一种用于设计集成电路（IC）的优化规范的方法和系统。 IC包括多个单元，并且每个单元包括多个晶体管。该方法包括准备多个设备中的至少一个设备的线宽图，基于线宽图执行至少一个设备的地形感知分析，以及基于地形感知来设计IC的优化规范分析。在另一个实施例中，提供了一种用于估计IC中的至少一个设备的泄漏功率的方法。该方法包括确定散焦和音调值，基于散焦和音调值确定线宽值，以及基于线宽值估计泄漏电流和/或泄漏功率。

5. 发明授权

US08745553B2 Method and apparatus for applying post graphic data system stream enhancements 有权
标题翻译：应用后图形数据系统流增强的方法和装置
公开(公告)号：US08745553B2
公开(公告)日：2014-06-03
申请号：US13592434
申请日：2012-08-23
申请人： Swamy Muddu , Sriram Madhavan , Shobhit Malik
发明人： Swamy Muddu , Sriram Madhavan , Shobhit Malik
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265 , Y02T10/82
摘要： An approach is provided for applying post graphic data system (GDS) stream enhancements back to the design stage. Embodiments include receiving a data stream of an integrated circuit design layout from a design stage, determining one or more design constructs based on an analysis of the data stream, determining one or more instructions to implement the one or more design constructs at the design stage, and sending the instructions to the design stage to implement the one or more design constructs.
摘要翻译：提供了一种将后图形数据系统（GDS）流增强功能应用于设计阶段的方法。实施例包括从设计阶段接收集成电路设计布局的数据流，基于数据流的分析确定一个或多个设计构造，确定在设计阶段实现一个或多个设计构造的一个或多个指令，并将指令发送到设计阶段以实现一个或多个设计构造。

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