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1. 发明申请

US20110286511A1 DATA LATCH CIRCUIT AND METHOD OF A LOW POWER DECISION FEEDBACK EQUALIZATION (DFE) SYSTEM 有权
公开(公告)号：US20110286511A1
公开(公告)日：2011-11-24
申请号：US12949838
申请日：2010-11-19
申请人： YI ZENG , Freeman Zhong , Peter Windler
发明人： YI ZENG , Freeman Zhong , Peter Windler
IPC分类号： H03H7/40
CPC分类号： H04L25/03057 , H04L25/0274
摘要： Data latch circuit and method of low power decision feedback equalization (DFE) system is disclosed. In one embodiment, the data latch circuit of the of a decision feedback equalization (DFE) system includes a first parallel n-channel metal-oxide-semiconductor field-effect transistor (NMOS) pair to input a differential input voltage. The data latch circuit also includes a second parallel NMOS pair coupled to the first parallel NMOS pair to input a decision feedback equalization (DFE) voltage. The data latch circuit further includes a cross-coupled PMOS pair to generate a positive feedback to the first parallel NMOS pair and/or the second parallel NMOS pair. In addition, the data latch circuit includes a cross-coupled NMOS pair to escalate the positive feedback. Furthermore the data latch circuit includes a latching circuit to generate a signal data based on the sinking of a current at an input of the latching circuit and/or the positive feedback.

2. 发明申请

US20080070537A1 Duty cycle counting phase calibration scheme of an I/O interface 有权
标题翻译： I / O接口的占空比计数相位校准方案
公开(公告)号：US20080070537A1
公开(公告)日：2008-03-20
申请号：US11516382
申请日：2006-09-05
申请人： Cathy Ye Lin , Freeman Zhong , Catherine Chow , Yi Zeng , Ryan Park
发明人： Cathy Ye Lin , Freeman Zhong , Catherine Chow , Yi Zeng , Ryan Park
IPC分类号： H04B7/00
CPC分类号： H03L7/06 , H04L7/0337
摘要： A method, apparatus and/or system of a duty cycle counting phase calibration scheme of an I/O interface is disclosed. In one embodiment a control unit of a communication system exchanging a multiple-phase time-interleaved data includes a first-PLL to generate a set of un-calibrated multiple-phase signals of a first-clock; a second-PLL, a pulse generator, a pulse-width measurement unit and a phase calibration engine to evaluate adjustments required in a temporal location of a logically critical voltage transition edge in each signal in the un-calibrated set; and a phase adjustment unit to adjust the temporal location of the logically critical voltage transition edge in each signal in the un-calibrated set to generate a set of calibrated multiple-phase signals of the first-clock such that each signal in the calibrated set includes the logically critical voltage transition edge which is time skewed in a predetermined amount from the logically critical voltage transition edge in other signals in the same set within a predetermined accuracy.
摘要翻译：公开了一种I / O接口的占空比计数相位校准方案的方法，装置和/或系统。在一个实施例中，交换多相时间交织数据的通信系统的控制单元包括第一PLL以产生第一时钟的一组未校准的多相信号; 第二PLL，脉冲发生器，脉冲宽度测量单元和相位校准引擎，用于评估未校准组中每个信号中的逻辑临界电压转变边缘的时间位置所需的调节; 以及相位调整单元，用于调整未校准组中每个信号中的逻辑关键电压转变边沿的时间位置，以产生第一时钟的一组经校准的多相信号，使得校准组中的每个信号包括逻辑临界电压转换边缘，其在预定精度内以相同组中的其他信号中的逻辑临界电压转变边缘以预定量时间偏斜。

3. 发明授权

US08437388B2 Data latch circuit and method of a low power decision feedback equalization (DFE) system 有权
标题翻译：数据锁存电路和低功率判决反馈均衡（DFE）系统的方法
公开(公告)号：US08437388B2
公开(公告)日：2013-05-07
申请号：US12949838
申请日：2010-11-19
申请人： Yi Zeng , Freeman Zhong , Peter Windler
发明人： Yi Zeng , Freeman Zhong , Peter Windler
IPC分类号： H03H7/40
CPC分类号： H04L25/03057 , H04L25/0274
摘要： Data latch circuit and method of low power decision feedback equalization (DFE) system is disclosed. In one embodiment, the data latch circuit of the of a decision feedback equalization (DFE) system includes a first parallel n-channel metal-oxide-semiconductor field-effect transistor (NMOS) pair to input a differential input voltage. The data latch circuit also includes a second parallel NMOS pair coupled to the first parallel NMOS pair to input a decision feedback equalization (DFE) voltage. The data latch circuit further includes a cross-coupled PMOS pair to generate a positive feedback to the first parallel NMOS pair and/or the second parallel NMOS pair. In addition, the data latch circuit includes a cross-coupled NMOS pair to escalate the positive feedback. Furthermore the data latch circuit includes a latching circuit to generate a signal data based on the sinking of a current at an input of the latching circuit and/or the positive feedback.
摘要翻译：公开了低功率判决反馈均衡（DFE）系统的数据锁存电路及方法。在一个实施例中，判决反馈均衡（DFE）系统的数据锁存电路包括第一并行n沟道金属氧化物半导体场效应晶体管（NMOS）对，以输入差分输入电压。数据锁存电路还包括耦合到第一并联NMOS对的第二并联NMOS对以输入判决反馈均衡（DFE）电压。数据锁存电路还包括交叉耦合PMOS对以产生对第一并联NMOS对和/或第二并联NMOS对的正反馈。此外，数据锁存电路包括交叉耦合的NMOS对以升级正反馈。此外，数据锁存电路包括一个锁存电路，用于基于在锁存电路的输入处的电流的吸收和/或正反馈来产生信号数据。

4. 发明授权

US07940140B2 Self-calibrated wide range LC tank voltage-controlled oscillator (VCO) system with expanded frequency tuning range and method for providing same 有权
标题翻译：自校准的宽范围LC箱压控振荡器（VCO）系统具有扩展的频率调谐范围和提供相同的方法
公开(公告)号：US07940140B2
公开(公告)日：2011-05-10
申请号：US12156607
申请日：2008-06-03
申请人： Yi Zeng , Freeman Zhong
发明人： Yi Zeng , Freeman Zhong
IPC分类号： H03L7/099 , H03L1/00 , H03B5/08
CPC分类号： H03L7/099 , H03B5/1215 , H03B5/1228 , H03B5/1253 , H03B5/1265
摘要： The present invention is a self-calibrating, dual-band, wide range LC tank Voltage Controlled Oscillator (VCO) system. The system may include a first Voltage-Controlled Oscillator (VCO) and a second Voltage-Controlled Oscillator (VCO). The system may further include a calibration engine. The calibration engine may be configured for being connectable to at least one of the first VCO or the second VCO. The calibration engine may further be configured for automatically establishing/providing a VCO fix capacitor band code setting and a gear control setting for selectively activating or inactivating the first VCO and/or the second VCO. The calibration engine may be further configured for automatically comparing a VCO control voltage of the system to an allowable control voltage range for the system and may be further configured for automatically adjusting the VCO fix capacitor band code setting and/or the gear control setting when the VCO control voltage falls outside of the allowable control voltage range.
摘要翻译：本发明是一种自校准的双频宽范围LC槽压控振荡器（VCO）系统。该系统可以包括第一电压控制振荡器（VCO）和第二电压控制振荡器（VCO）。该系统还可以包括校准引擎。校准引擎可以被配置为可连接到第一VCO或第二VCO中的至少一个。校准引擎还可以被配置为自动建立/提供VCO固定电容器频带码设置和齿轮控制设置，用于选择性地激活或失活第一VCO和/或第二VCO。校准引擎可以被进一步配置用于将系统的VCO控制电压自动地与系统的允许控制电压范围进行比较，并且还可以被配置为在自动调整VCO固定电容器频带代码设置和/或齿轮控制设置时 VCO控制电压超出允许的控制电压范围。

5. 发明授权

US07869498B2 Low power decision feedback equalization (DFE) through applying DFE data to input data in a data latch 有权
标题翻译：通过将DFE数据应用于数据锁存器中的输入数据，实现低功率判决反馈均衡（DFE）
公开(公告)号：US07869498B2
公开(公告)日：2011-01-11
申请号：US11709568
申请日：2007-02-21
申请人： Yi Zeng , Freeman Zhong , Peter Windler
发明人： Yi Zeng , Freeman Zhong , Peter Windler
IPC分类号： H03H7/40
CPC分类号： H04L25/03057 , H04L25/0274
摘要： Low power decision feedback equalization (DFE) through applying DFE data to input data in a data latch is disclosed. In one embodiment, a decision feedback equalization (DFE) system to remove a post cursor intersymbol interference (ISI) through feeding back previous data scaled with adaptive weights to the DFE system, with each slice of the DFE system may include a first set of decision feedback digital to analog converters (DACs) to generate a first DFE data obtained through the feeding back the previous data scaled with the adaptive weights and a first data latch to generate an output data of the each slice through applying the first DFE data to an input data of the each slice in the first data latch to remove a first delay caused by performing the applying the first DFE data to the input data of the each slice outside of the first data latch.
摘要翻译：公开了通过将DFE数据应用于数据锁存器中的输入数据的低功率判决反馈均衡（DFE）。在一个实施例中，一个判决反馈均衡（DFE）系统，通过将具有自适应权重的先前数据反馈到DFE系统来消除后光标符号间干扰（ISI），DFE系统的每个切片可以包括第一组决策反馈数模转换器（DAC）以产生通过反馈用自适应权重缩放的先前数据而获得的第一DFE数据和第一数据锁存器，以通过将第一DFE数据应用于输入来产生每个片的输出数据在第一数据锁存器中的每个片的数据，以消除通过执行将第一DFE数据应用于第一数据锁存器外的每个片的输入数据而引起的第一延迟。

6. 发明授权

US07688928B2 Duty cycle counting phase calibration scheme of an input/output (I/O) interface 有权
标题翻译：输入/输出（I / O）接口的占空比计数相位校准方案
公开(公告)号：US07688928B2
公开(公告)日：2010-03-30
申请号：US11516382
申请日：2006-09-05
申请人： Cathy Ye Lin , Freeman Zhong , Catherine Chow , Yi Zeng , Ryan Park
发明人： Cathy Ye Lin , Freeman Zhong , Catherine Chow , Yi Zeng , Ryan Park
IPC分类号： H03D3/24
CPC分类号： H03L7/06 , H04L7/0337
摘要： In one embodiment a control unit of a communication system exchanging a multiple-phase time-interleaved data includes a first Phase-Locked Loop (PLL) to generate a set of un-calibrated multiple-phase signals of a first-clock; a second-PLL, a pulse generator, a pulse-width measurement unit and a phase calibration engine to evaluate adjustments required in a temporal location of a logically critical voltage transition edge in each signal in the un-calibrated set; and a phase adjustment unit to adjust the temporal location of the logically critical voltage transition edge in each signal in the un-calibrated set to generate a set of calibrated multiple-phase signals of the first-clock such that each signal in the calibrated set includes the logically critical voltage transition edge which is time skewed in a predetermined amount from the logically critical voltage transition edge in other signals in the same set within a predetermined accuracy.
摘要翻译：在一个实施例中，交换多相时间交织数据的通信系统的控制单元包括：第一锁相环（PLL），用于产生一组未校准的第一时钟的多相信号; 第二PLL，脉冲发生器，脉冲宽度测量单元和相位校准引擎，用于评估未校准组中每个信号中的逻辑临界电压转变边缘的时间位置所需的调节; 以及相位调整单元，用于调整未校准组中每个信号中的逻辑关键电压转变边沿的时间位置，以产生第一时钟的一组经校准的多相信号，使得校准组中的每个信号包括逻辑临界电压转换边缘，其在预定精度内以相同组中的其他信号中的逻辑临界电压转变边缘以预定量时间偏斜。

7. 发明申请

US20090295488A1 Self-calibrated wide range LC tank voltage-controlled oscillator (VCO) system with expanded frequency tuning range and method for providing same 有权
标题翻译：自校准的宽范围LC箱压控振荡器（VCO）系统具有扩展的频率调谐范围和提供相同的方法
公开(公告)号：US20090295488A1
公开(公告)日：2009-12-03
申请号：US12156607
申请日：2008-06-03
申请人： Yi Zeng , Freeman Zhong
发明人： Yi Zeng , Freeman Zhong
IPC分类号： H03L7/00
CPC分类号： H03L7/099 , H03B5/1215 , H03B5/1228 , H03B5/1253 , H03B5/1265
摘要： The present invention is a self-calibrating, dual-band, wide range LC tank Voltage Controlled Oscillator (VCO) system. The system may include a first Voltage-Controlled Oscillator (VCO) and a second Voltage-Controlled Oscillator (VCO). The system may further include a calibration engine. The calibration engine may be configured for being connectable to at least one of the first VCO or the second VCO. The calibration engine may further be configured for automatically establishing/providing a VCO fix capacitor band code setting and a gear control setting for selectively activating or inactivating the first VCO and/or the second VCO. The calibration engine may be further configured for automatically comparing a VCO control voltage of the system to an allowable control voltage range for the system and may be further configured for automatically adjusting the VCO fix capacitor band code setting and/or the gear control setting when the VCO control voltage falls outside of the allowable control voltage range.
摘要翻译：本发明是一种自校准的双频宽范围LC槽压控振荡器（VCO）系统。该系统可以包括第一电压控制振荡器（VCO）和第二电压控制振荡器（VCO）。该系统还可以包括校准引擎。校准引擎可以被配置为可连接到第一VCO或第二VCO中的至少一个。校准引擎还可以被配置为自动建立/提供VCO固定电容器频带码设置和齿轮控制设置，用于选择性地激活或失活第一VCO和/或第二VCO。校准引擎可以被进一步配置用于将系统的VCO控制电压自动地与系统的允许控制电压范围进行比较，并且还可以被配置为在自动调整VCO固定电容器频带代码设置和/或齿轮控制设置时 VCO控制电压超出允许的控制电压范围。

8. 发明申请

US20080198916A1 Low power decision feedback equalization (DFE) through applying DFE data to input data in a data latch 有权
标题翻译：通过将DFE数据应用于数据锁存器中的输入数据，实现低功率判决反馈均衡（DFE）
公开(公告)号：US20080198916A1
公开(公告)日：2008-08-21
申请号：US11709568
申请日：2007-02-21
申请人： Yi Zeng , Freeman Zhong , Peter Windler
发明人： Yi Zeng , Freeman Zhong , Peter Windler
IPC分类号： H03K5/159
CPC分类号： H04L25/03057 , H04L25/0274
摘要： Low power decision feedback equalization (DFE) through applying DFE data to input data in a data latch is disclosed. In one embodiment, a decision feedback equalization (DFE) system to remove a post cursor intersymbol interference (ISI) through feeding back previous data scaled with adaptive weights to the DFE system, with each slice of the DFE system may include a first set of decision feedback digital to analog converters (DACs) to generate a first DFE data obtained through the feeding back the previous data scaled with the adaptive weights and a first data latch to generate an output data of the each slice through applying the first DFE data to an input data of the each slice in the first data latch to remove a first delay caused by performing the applying the first DFE data to the input data of the each slice outside of the first data latch.
摘要翻译：公开了通过将DFE数据应用于数据锁存器中的输入数据的低功率判决反馈均衡（DFE）。在一个实施例中，一个判决反馈均衡（DFE）系统，通过将具有自适应权重的先前数据反馈到DFE系统来消除后光标符号间干扰（ISI），DFE系统的每个切片可以包括第一组决策反馈数模转换器（DAC）以产生通过反馈用自适应权重缩放的先前数据而获得的第一DFE数据和第一数据锁存器，以通过将第一DFE数据应用于输入来产生每个片的输出数据在第一数据锁存器中的每个片的数据，以消除通过执行将第一DFE数据应用于第一数据锁存器外的每个片的输入数据而引起的第一延迟。

9. 发明申请

US20070139078A1 PCML driver for LVDS receiver loads 审中-公开
标题翻译：用于LVDS接收器负载的PCML驱动程序
公开(公告)号：US20070139078A1
公开(公告)日：2007-06-21
申请号：US11314768
申请日：2005-12-20
申请人： George Tang , Freeman Zhong
发明人： George Tang , Freeman Zhong
IPC分类号： H03K19/094
CPC分类号： H03K19/018528
摘要： The improved PCML communications driver corrects current loss and reduced voltage swing when driving an LVDS receiver load by reducing the value of the Rt1 resistors. By changing the value of the two Rt1 resistors from Rt1 to Rt1/2 (or lower), the full bias current can be restored and voltage swing is substantially improved. By making Rt1 a programmable resistor so Rt=Rt1/2 for DC bias calculation, Q2 bias current is increased back to IB, instead of IB/2.
摘要翻译：改进的PCML通信驱动器通过降低Rt 1电阻的值来校正当驱动LVDS接收器负载时的电流损耗和降低的电压摆幅。通过将两个Rt 1电阻器的值从Rt 1改变为Rt 1/2（或更低），可以恢复全偏置电流，并显着提高电压摆幅。通过使Rt 1成为可编程电阻器，因此对于直流偏置计算，Rt = Rt 1/2，Q 2偏置电流增加到IB，而不是IB / 2。

10. 发明授权

US6005429A I.sub.cc current electromagnetic interference choke with multiple choking levels 失效
标题翻译： Icc当前电磁干扰扼流圈有多个阻塞水平
公开(公告)号：US6005429A
公开(公告)日：1999-12-21
申请号：US118283
申请日：1998-07-17
申请人： Freeman Zhong , William E. Miller
发明人： Freeman Zhong , William E. Miller
IPC分类号： H03K17/16 , H03K5/14
CPC分类号： H03K17/164
摘要： An apparatus for and method of reducing electromagnetic interference of an integrated circuit by providing multiple choking levels are disclosed. A choking circuit includes a choking level select signal generator, a pulse choking circuit connected to the choking level select signal generator, and a modulation control circuit connected to the pulse choking circuit. The choking level is increased when modules of the integrated circuit are less active, which reduces electromagnetic interference. The choking level is decreased when modules of the integrated circuit are more active, which maintains the voltage supplied to the power bus above a desired level.
摘要翻译：公开了一种通过提供多个阻塞水平来降低集成电路的电磁干扰的装置和方法。扼流电路包括扼流电平选择信号发生器，连接到扼流电平选择信号发生器的脉冲阻塞电路，以及连接到脉冲阻塞电路的调制控制电路。当集成电路的模块活动较少时，阻塞水平增加，这降低了电磁干扰。当集成电路的模块更有效时，阻塞水平降低，这将提供给电力总线的电压保持在所需的水平以上。

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