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1. 发明申请

US20100156686A1 PULSE GENERATOR AND CONTINUOUS-TIME SIGMA-DELTA MODULATOR 有权
标题翻译：脉冲发生器和连续时间信号调制器
公开(公告)号：US20100156686A1
公开(公告)日：2010-06-24
申请号：US12509152
申请日：2009-07-24
申请人： Yi Gyeong KIM , Min Hyung Cho , Jong Kee Kwon
发明人： Yi Gyeong KIM , Min Hyung Cho , Jong Kee Kwon
IPC分类号： H03M3/02
CPC分类号： H03M3/372 , H03K3/3565 , H03M3/43 , H03M3/454
摘要： Provided is a clock generator employed in a continuous-time sigma-delta modulator. The clock generator includes an oscillator configured to generate pulses in response to an enable signal, a counter configured to count the number of pulses generated by the oscillator and output the total pulse count, and an output circuit configured to output an inactivated output signal if the pulse count of the counter is equal to a pulse-width control bit. The oscillator includes an astable multi-vibrator. Since the astable multi-vibrator capable of generating a low-jitter pulse from a jittered clock is used as the oscillator, a signal-to-noise ratio is improved. A simple configuration using only digital circuits makes it easier to design a circuit and adjust pulse width. Moreover, according to the structure of the astable multi-vibrator, it is possible to design a circuit to optimally modulate pulse width in connection with process variations of resistors and capacitors used in the continuous-time sigma-delta modulator.
摘要翻译：提供了一种在连续时间Σ-Δ调制器中使用的时钟发生器。所述时钟发生器包括被配置为响应于使能信号产生脉冲的振荡器，被配置为对所述振荡器产生的脉冲数进行计数并输出所述总脉冲计数的计数器;以及输出电路，其配置为：如果计数器的脉冲计数等于脉冲宽度控制位。该振荡器包括一个不稳定的多重振动器。由于能够从抖动时钟产生低抖动脉冲的不稳定的多重振动器被用作振荡器，所以提高了信噪比。仅使用数字电路的简单配置使得更容易设计电路并调整脉冲宽度。此外，根据不稳定的多振子的结构，可以设计电路，以便在连续时间Σ-Δ调制器中使用的电阻器和电容器的工艺变化方面最佳地调制脉冲宽度。

2. 发明授权

US08199038B2 Active resistance-capacitor integrator and continuous-time sigma-delta modulator with gain control function 有权
标题翻译：有源电阻电容积分器和具有增益控制功能的连续时间Σ-Δ调制器
公开(公告)号：US08199038B2
公开(公告)日：2012-06-12
申请号：US12843591
申请日：2010-07-26
申请人： Yi Gyeong Kim , Min Hyung Cho , Jong Kee Kwon
发明人： Yi Gyeong Kim , Min Hyung Cho , Jong Kee Kwon
IPC分类号： H03M3/00
CPC分类号： G06G7/186 , H03M3/43 , H03M3/454 , H03M3/486
摘要： Provided are an active resistance-capacitance (RC) integrator and a continuous-time sigma-delta modulator, which have a gain control function. The active RC integrator includes an amplifier, a first base resistor connected between a first input node and a positive input port of the amplifier, a second base resistor connected between a second input node and a negative input port of the amplifier, a first resistor unit connected between the second input node and the positive input port of the amplifier, and a second resistor unit connected between the first input node and the negative input port of the amplifier. A resistor network including resistors and switches is configured to vary an input resistance, so that an active RC integrator may have a gain control function.
摘要翻译：提供了具有增益控制功能的有源电阻 - 电容（RC）积分器和连续时间Σ-Δ调制器。有源RC积分器包括放大器，连接在放大器的第一输入节点和正输入端口之间的第一基极电阻器，连接在放大器的第二输入节点和负输入端口之间的第二基极电阻器，第一电阻器单元连接在放大器的第二输入节点和正输入端口之间，以及连接在放大器的第一输入节点和负输入端口之间的第二电阻器单元。包括电阻器和开关的电阻器网络被配置为改变输入电阻，使得有源RC积分器可以具有增益控制功能。

3. 发明授权

US07961128B2 Pulse generator and continuous-time sigma-delta modulator 有权
标题翻译：脉冲发生器和连续时间Σ-Δ调制器
公开(公告)号：US07961128B2
公开(公告)日：2011-06-14
申请号：US12509152
申请日：2009-07-24
申请人： Yi Gyeong Kim , Min Hyung Cho , Jong Kee Kwon
发明人： Yi Gyeong Kim , Min Hyung Cho , Jong Kee Kwon
IPC分类号： H03M3/00
CPC分类号： H03M3/372 , H03K3/3565 , H03M3/43 , H03M3/454
摘要： Provided is a clock generator employed in a continuous-time sigma-delta modulator. The clock generator includes an oscillator configured to generate pulses in response to an enable signal, a counter configured to count the number of pulses generated by the oscillator and output the total pulse count, and an output circuit configured to output an inactivated output signal if the pulse count of the counter is equal to a pulse-width control bit. The oscillator includes an astable multi-vibrator. Since the astable multi-vibrator capable of generating a low-jitter pulse from a jittered clock is used as the oscillator, a signal-to-noise ratio is improved. A simple configuration using only digital circuits makes it easier to design a circuit and adjust pulse width. Moreover, according to the structure of the astable multi-vibrator, it is possible to design a circuit to optimally modulate pulse width in connection with process variations of resistors and capacitors used in the continuous-time sigma-delta modulator.
摘要翻译：提供了一种在连续时间Σ-Δ调制器中使用的时钟发生器。所述时钟发生器包括被配置为响应于使能信号产生脉冲的振荡器，被配置为对所述振荡器产生的脉冲数进行计数并输出所述总脉冲计数的计数器;以及输出电路，其配置为：如果计数器的脉冲计数等于脉冲宽度控制位。该振荡器包括一个不稳定的多重振动器。由于能够从抖动时钟产生低抖动脉冲的不稳定的多重振动器被用作振荡器，所以提高了信噪比。仅使用数字电路的简单配置使得更容易设计电路并调整脉冲宽度。此外，根据不稳定的多振子的结构，可以设计电路，以便在连续时间Σ-Δ调制器中使用的电阻器和电容器的工艺变化方面最佳地调制脉冲宽度。

4. 发明授权

US08164491B2 Coefficient multiplier and digital delta-sigma modulator using the same 有权
标题翻译：系数乘法器和使用其的数字delta-sigma调制器
公开(公告)号：US08164491B2
公开(公告)日：2012-04-24
申请号：US12783294
申请日：2010-05-19
申请人： Min Hyung Cho , Yi Gyeong Kim , Jong Kee Kwon
发明人： Min Hyung Cho , Yi Gyeong Kim , Jong Kee Kwon
IPC分类号： H03M7/32
CPC分类号： H03M7/3004 , H03M7/3033 , H03M7/304
摘要： Provided are a coefficient multiplier and digital delta-sigma modulator using the same. The coefficient multiplier has the average of output signals of respective dependent multipliers as an effective coefficient using a coefficient averaging technique without employing an adder that has a complex structure and occupies a large chip area. Accordingly, the coefficient multiplier has a simple hardware constitution and small chip area in comparison with a canonical signed digit (CSD) coefficient multiplier, and the digital delta-sigma modulator employing the coefficient multiplier has a simple structure and small size.
摘要翻译：提供了使用其的系数乘法器和数字Δ-Σ调制器。系数乘法器使用系数平均技术将各自的相关乘法器的输出信号的平均值作为有效系数，而不使用具有复杂结构的加法器并占据较大的码片面积。因此，系数乘法器与典型有符号数（CSD）系数乘法器相比，具有简单的硬件结构和小的芯片面积，并且采用系数乘法器的数字Δ-Σ调制器结构简单，体积小。

5. 发明授权

US07821341B2 Gain control device and amplifier using the same 有权
标题翻译：增益控制装置和放大器使用相同
公开(公告)号：US07821341B2
公开(公告)日：2010-10-26
申请号：US12507701
申请日：2009-07-22
申请人： Yi Gyeong Kim , Min Hyung Cho , Jong Kee Kwon
发明人： Yi Gyeong Kim , Min Hyung Cho , Jong Kee Kwon
IPC分类号： H03G3/10
CPC分类号： H03F3/45475 , H03F2203/45528 , H03F2203/45591
摘要： Provided are a gain control device and an amplifier using the gain control device. The gain control device includes a first input resistance unit having a first variable resistor whose resistance is linearly variable and a first fixed resistor respectively receiving a first input signal and a second input signal having a sign different from the first input signal and outputting current through a first output terminal, and a second input resistance unit having a second fixed resistor and a second variable resistor whose resistance is linearly variable respectively receiving the first input signal and the second input signal and outputting current through a second output terminal.Since the gain control device can separately perform dB-linear gain control, it is easily combined with a circuit, such as a continuous-time sigma-delta modulator (SDM), a continuous-time filter, and a continuous-time analog-to-digital converter (ADC), and enables miniaturization and low power consumption.
摘要翻译：提供了增益控制装置和使用增益控制装置的放大器。所述增益控制装置包括具有电阻为线性变化的第一可变电阻器和分别接收第一输入信号的第一固定电阻器和具有与第一输入信号不同的符号的第二输入信号的第一输入电阻单元，第一输出端子和具有第二固定电阻器和第二可变电阻器的第二输入电阻单元，其电阻为线性变化，分别接收第一输入信号和第二输入信号，并通过第二输出端子输出电流。由于增益控制装置可以单独执行dB线性增益控制，所以可以容易地与诸如连续时间Σ-Δ调制器（SDM），连续时间滤波器以及连续时间模拟到数字转换器（ADC），并实现小型化和低功耗。

6. 发明授权

US08300850B2 Read-out circuit with high input impedance 有权
标题翻译：具有高输入阻抗的读出电路
公开(公告)号：US08300850B2
公开(公告)日：2012-10-30
申请号：US12511361
申请日：2009-07-29
申请人： Min Hyung Cho , Yi Gyeong Kim , Jae Won Nam , Jong Kee Kwon
发明人： Min Hyung Cho , Yi Gyeong Kim , Jae Won Nam , Jong Kee Kwon
IPC分类号： H04R3/00
CPC分类号： H04R3/00
摘要： Provided is a read-out circuit that is connected to a microphone and configured to linearly amplify a current signal generated by the microphone and output the amplified current signal. The read-out circuit includes an amplification unit and a feedback resistor. The amplification unit has an amplification gain between 0 and 1. The feedback resistor is connected between input and output terminals of the amplification unit. As the amplification gain of the amplification unit becomes closer to 1, an input impedance becomes higher. A preamp of the read-out circuit can have a high input impedance due to the amplification gain, and the read-out circuit can be manufactured using a CMOS process.
摘要翻译：提供了一种连接到麦克风并被配置为线性放大由麦克风产生的电流信号并输出放大的电流信号的读出电路。读出电路包括放大单元和反馈电阻器。放大单元的放大增益在0和1之间。反馈电阻连接在放大单元的输入和输出端之间。随着放大单元的放大增益变得更接近于1，输入阻抗变高。由于放大增益，读出电路的前置放大器可以具有高输入阻抗，并且读出电路可以使用CMOS工艺制造。

7. 发明申请

US20070126615A1 Multi-bit sigma-delta modulator and digital-to-analog converter with one digital-to-analog capacitor 有权
标题翻译：多位Σ-Δ调制器和具有一个数模转换器的数/模转换器
公开(公告)号：US20070126615A1
公开(公告)日：2007-06-07
申请号：US11588455
申请日：2006-10-27
申请人： Yi Gyeong Kim , Chong Ki Kwon , Jong Dae Kim , Min Hyung Cho , Seung Chul Lee , Gyu Hyun Kim
发明人： Yi Gyeong Kim , Chong Ki Kwon , Jong Dae Kim , Min Hyung Cho , Seung Chul Lee , Gyu Hyun Kim
IPC分类号： H03M1/66
CPC分类号： H03M3/352 , H03M3/424 , H03M3/464
摘要： A digital-to-analog converter (DAC) for a sigma-delta modulator is provided. The DAC has a switched capacitor structure using an operational amplifier (OP amp) and performs a function exceeding 3-level using a switching method employing only one capacitor in single ended form. Thus, DAC non-linearity caused by capacitor mismatching does not occur, and the number of output levels of the DAC is increased. Also, the DAC capacitor may be applied to a general DAC to increase the ratio of DAC output levels to capacitors.
摘要翻译：提供了一种用于Σ-Δ调制器的数模转换器（DAC）。 DAC具有使用运算放大器（OP放大器）的开关电容器结构，并且使用仅采用单端形式的一个电容器的开关方法来执行超过3电平的功能。因此，不会发生由电容器失配引起的DAC非线性，并且DAC的输出电平的数量增加。此外，DAC电容器可以被施加到通用DAC以增加DAC输出电平与电容器的比率。

8. 发明申请

US20090121909A1 DYNAMIC ELEMENT-MATCHING METHOD, MULTI-BIT DAC USING THE METHOD, AND DELTA-SIGMA MODULATOR AND DELTA-SIGMA DAC INCLUDING THE MULTI-BIT DAC 有权
标题翻译：使用该方法的动态元件匹配方法，多位DAC，以及包括多位DAC的DELTA-SIGMA调制器和DELTA-SIGMA DAC
公开(公告)号：US20090121909A1
公开(公告)日：2009-05-14
申请号：US12195232
申请日：2008-08-20
申请人： Yi Gyeong KIM , Min Hyung Cho , Chong Ki Kwon
发明人： Yi Gyeong KIM , Min Hyung Cho , Chong Ki Kwon
IPC分类号： H03M3/00 , H03M1/66 , H03M1/80
CPC分类号： H03M1/0665 , H03M1/74 , H03M3/464 , H03M3/502
摘要： Provided are a dynamic element-matching method, a multi-bit Digital-to-Analog Converter (DAC), and a delta-sigma modulator with the multi-bit DAC and delta-sigma DAC with the multi-bit DAC. The dynamic element-matching method relates to preventing periodic signal components (in-band tones) from being generated from a delta-sigma modulator of a delta-sigma Analog-to-Digital Converter (ADC) and a multi-bit DAC used in a delta-sigma DAC. Unit elements are selected in a new sequence according to a simple algorithm every time that each of unit elements is selected once, and thus the unit elements are not periodically used. Consequently, it is possible to prevent in-band tones caused by a conventional Data Weighted Averaging (DWA) algorithm.
摘要翻译：提供了动态元件匹配方法，多位数模转换器（DAC）和具有多位DAC的多位DAC和Δ-ΣDAC的Δ-Σ调制器。动态元件匹配方法涉及防止从Δ-Σ模数转换器（ADC）的delta-sigma调制器和用于在A-Sigma模数转换器（ADC）中使用的多位DAC的周期性信号分量（带内音调） Δ-ΣDAC。每次选择一个单位元素一次时，根据简单算法以新的顺序选择单位元素，因此单位元素不被周期性地使用。因此，可以防止由传统的数据加权平均（DWA）算法引起的带内音调。

9. 发明授权

US07388533B2 Multi-bit sigma-delta modulator and digital-to-analog converter with one digital-to-analog capacitor 有权
标题翻译：多位Σ-Δ调制器和具有一个数模转换器的数/模转换器
公开(公告)号：US07388533B2
公开(公告)日：2008-06-17
申请号：US11588455
申请日：2006-10-27
申请人： Yi Gyeong Kim , Chong Ki Kwon , Jong Dae Kim , Min Hyung Cho , Seung Chul Lee , Gyu Hyun Kim
发明人： Yi Gyeong Kim , Chong Ki Kwon , Jong Dae Kim , Min Hyung Cho , Seung Chul Lee , Gyu Hyun Kim
IPC分类号： H03M1/82 , H03M3/00
CPC分类号： H03M3/352 , H03M3/424 , H03M3/464
摘要： A digital-to-analog converter (DAC) for a sigma-delta modulator is provided. The DAC has a switched capacitor structure using an operational amplifier (OP amp) and performs a function exceeding 3-level using a switching method employing only one capacitor in single ended form. Thus, DAC non-linearity caused by capacitor mismatching does not occur, and the number of output levels of the DAC is increased. Also, the DAC capacitor may be applied to a general DAC to increase the ratio of DAC output levels to capacitors.
摘要翻译：提供了一种用于Σ-Δ调制器的数模转换器（DAC）。 DAC具有使用运算放大器（OP放大器）的开关电容器结构，并且使用仅采用单端形式的一个电容器的开关方法来执行超过3电平的功能。因此，不会发生由电容器失配引起的DAC非线性，并且DAC的输出电平的数量增加。此外，DAC电容器可以被施加到通用DAC以增加DAC输出电平与电容器的比率。

10. 发明授权

US07719455B2 Dynamic element-matching method, multi-bit DAC using the method, and delta-sigma modulator and delta-sigma DAC including the multi-bit DAC 有权
标题翻译：动态元件匹配方法，使用该方法的多位DAC，以及包括多位DAC的Δ-Σ调制器和Δ-ΣDAC
公开(公告)号：US07719455B2
公开(公告)日：2010-05-18
申请号：US12195232
申请日：2008-08-20
申请人： Yi Gyeong Kim , Min Hyung Cho , Chong Ki Kwon
发明人： Yi Gyeong Kim , Min Hyung Cho , Chong Ki Kwon
IPC分类号： H03M1/66
CPC分类号： H03M1/0665 , H03M1/74 , H03M3/464 , H03M3/502
摘要： Provided are a dynamic element-matching method, a multi-bit Digital-to-Analog Converter (DAC), and a delta-sigma modulator with the multi-bit DAC and delta-sigma DAC with the multi-bit DAC. The dynamic element-matching method relates to preventing periodic signal components (in-band tones) from being generated from a delta-sigma modulator of a delta-sigma Analog-to-Digital Converter (ADC) and a multi-bit DAC used in a delta-sigma DAC. Unit elements are selected in a new sequence according to a simple algorithm every time that each of unit elements is selected once, and thus the unit elements are not periodically used. Consequently, it is possible to prevent in-band tones caused by a conventional Data Weighted Averaging (DWA) algorithm.
摘要翻译：提供了动态元件匹配方法，多位数模转换器（DAC）和具有多位DAC的多位DAC和Δ-ΣDAC的Δ-Σ调制器。动态元件匹配方法涉及防止从Δ-Σ模数转换器（ADC）的delta-sigma调制器和用于在A-Sigma模数转换器（ADC）中使用的多位DAC的周期性信号分量（带内音调） Δ-ΣDAC。每次选择一个单位元素一次时，根据简单算法以新的顺序选择单位元素，因此单位元素不被周期性地使用。因此，可以防止由传统的数据加权平均（DWA）算法引起的带内音调。

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