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1. 发明授权

US5689258A Multiple current digital-analog converter capable of reducing output glitch 失效
标题翻译：多电流数字模拟转换器可以减少输出毛刺
公开(公告)号：US5689258A
公开(公告)日：1997-11-18
申请号：US532315
申请日：1995-09-21
申请人： Yasuyuki Nakamura , Hiroyuki Kouno , Takahiro Miki
发明人： Yasuyuki Nakamura , Hiroyuki Kouno , Takahiro Miki
IPC分类号： H03M1/08 , H03M1/74 , H03M1/66
CPC分类号： H03M1/0863 , H03M1/747
摘要： A digital-analog converter has unit current source cells each having a differential switch circuit and a constant current source. The differential switch circuit made of two switches is driven by a pair of complementary driving circuits controlled by a bit signal and the inverted bit signal corresponding to that signal and entered simultaneously. The constant current source outputs a constant current to a first and a second current output terminal via the switch circuit. The signals for controlling the driving circuits that drive the switches are such that the delay time for the switch closing operation will be longer than the delay time for the switch opening operation. As a result, the cross point of the two signals to open and close the switches in a complementary manner becomes greater than the median between the maximum and minimum signal levels. That is, even when the threshold value of a currently switching transistor is greater than a median, that value may be arranged to match the median, whereby the furnished switching transistors are not turned on or off simultaneously.
摘要翻译：数模转换器具有单元电流源单元，每个单元具有差分开关电路和恒流源。由两个开关构成的差分开关电路由一对由位信号控制的互补驱动电路和对应于该信号的反相位信号驱动并同时输入。恒流源通过开关电路向第一和第二电流输出端输出恒定电流。用于控制驱动开关的驱动电路的信号使得开关闭合操作的延迟时间将长于开关操作的延迟时间。结果，以互补方式打开和闭合开关的两个信号的交叉点变得大于最大和最小信号电平之间的中值。也就是说，即使当当前开关晶体管的阈值大于中值时，也可以将该值设置为与中值相匹配，由此所提供的开关晶体管不会同时导通或截止。

2. 发明授权

US5631579A Output buffer circuit for interfacing semiconductor integrated circuits operating on different supply voltages 失效
标题翻译：用于连接在不同电源电压下工作的半导体集成电路的输出缓冲电路
公开(公告)号：US5631579A
公开(公告)日：1997-05-20
申请号：US548066
申请日：1995-10-25
申请人： Takahiro Miki , Hiroyuki Kouno , Yasuyuki Nakamura
发明人： Takahiro Miki , Hiroyuki Kouno , Yasuyuki Nakamura
IPC分类号： G06F3/00 , G11C11/409 , H01L27/02 , H03K19/003 , H03K19/0175 , H03K19/0185
CPC分类号： H03K19/00315 , H01L27/0251
摘要： An output buffer circuit operating normally when its supply potential is exceeded by the potential of the bus to which the buffer circuit output is connected. The circuit comprises a p-channel MOS transistor and a first and a second n-channel MOS transistor. The output node of the output buffer circuit is connected not to the p-channel MOS transistor but to the connection point between the source of the first n-channel MOS transistor and the drain of the second n-channel MOS transistor. The threshold potential of the first n-channel MOS transistor is set so that, with the output node in the high-impedance state, the first n-channel MOS transistor is turned off when the output node potential exceeds the supply potential of the output buffer circuit. This prevents the p-channel MOS transistor from getting activated or from being forward-biased between the back gate and the drain or source. Thus no leak current flows when the bus potential becomes higher than the supply potential of the output buffer circuit.
摘要翻译：当缓冲电路输出的总线的电位超过其电源电位时，输出缓冲电路正常工作。电路包括p沟道MOS晶体管和第一和第二n沟道MOS晶体管。输出缓冲电路的输出节点不连接到p沟道MOS晶体管，而是连接到第一n沟道MOS晶体管的源极和第二n沟道MOS晶体管的漏极之间的连接点。第一n沟道MOS晶体管的阈值电位被设置为使得当输出节点处于高阻抗状态时，当输出节点电位超过输出缓冲器的供给电位时，第一n沟道MOS晶体管截止电路。这防止了p沟道MOS晶体管在背栅极和漏极或源极之间被激活或被正向偏置。因此，当总线电位变得高于输出缓冲电路的电源电位时，没有泄漏电流流动。

3. 发明授权

US06784548B2 Semiconductor device having dummy patterns for metal CMP 失效
标题翻译：具有用于金属CMP的虚设图案的半导体器件
公开(公告)号：US06784548B2
公开(公告)日：2004-08-31
申请号：US10309272
申请日：2002-12-04
申请人： Hiroyuki Kouno , Toshio Kumamoto , Takahiro Miki , Hisayasu Satoh
发明人： Hiroyuki Kouno , Toshio Kumamoto , Takahiro Miki , Hisayasu Satoh
IPC分类号： H01L2348
CPC分类号： H01L27/08 , H01L21/31053 , H01L21/76819 , H01L21/76838 , H01L21/823437 , H01L23/5227 , H01L23/528 , H01L29/42372 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A gate electrode has a relatively long gate length of e.g., about 10 &mgr;m. In a region immediately above the gate electrode which is sandwiched between first-layer metals provided is a metal dummy pattern having a width in the first direction and extending in the second direction perpendicular to a direction of gate length (direction of current flow). Moreover, a geometric center of the metal dummy pattern in the second direction is equal to a geometric center of the gate electrode in the second direction. This maintains the symmetry in shape of the metal dummy pattern as viewed from the gate electrode. Such a structure can make deterioration in characteristics of a plurality of elements uniform while maintaining the essential effect of a metal CMP.
摘要翻译：栅电极具有例如约10μm的较长栅极长度。在夹在所提供的第一层金属之间的栅电极正上方的区域是具有第一方向的宽度并且沿与栅极长度方向（电流方向）垂直的第二方向延伸的金属虚设图案。此外，第二方向上的金属虚设图案的几何中心等于栅电极在第二方向上的几何中心。这保持了从栅电极观察时的金属虚设图形的对称性。这种结构可以使多种元素的特性劣化，同时保持金属CMP的基本效果。

4. 发明授权

US5469047A Transistor circuit 失效
标题翻译：晶体管电路
公开(公告)号：US5469047A
公开(公告)日：1995-11-21
申请号：US311433
申请日：1994-09-26
申请人： Toshio Kumamoto , Takahiro Miki , Hiroyuki Kouno
发明人： Toshio Kumamoto , Takahiro Miki , Hiroyuki Kouno
IPC分类号： G05F3/16 , G05F3/20
CPC分类号： G05F3/20
摘要： In order to obtain a constant current circuit which has an excellent constant current property and requires no plural bias circuits, a base of an NPN bipolar transistor (5) and a gate of an N-channel MOS transistor (6) are connected to a first terminal (1) in common. A collector of the transistor (5) is connected to a second terminal (2) and a source of a transistor (6) is connected to a third terminal respectively, while a voltage source (59) is connected between the first and third terminals. An emitter of the transistor (5) is connected with a drain of the transistor (6). Identical bias voltages are supplied to the base and the gate, while a gate-to-drain voltage of the transistor (6) is equal to a base-to-emitter voltage of the transistor (5). Thus, the transistor (6) operates in a pentode region, to serve as a constant current load for the transistor (5).
摘要翻译：为了获得具有优异的恒定电流特性并且不需要多个偏置电路的恒流电路，NPN双极晶体管（5）的基极和N沟道MOS晶体管（6）的栅极连接到第一终端（1）共同点。晶体管（5）的集电极连接到第二端子（2），并且晶体管（6）的源极分别连接到第三端子，而电压源（59）连接在第一和第三端子之间。晶体管（5）的发射极与晶体管（6）的漏极连接。相同的偏置电压被提供给基极和栅极，而晶体管（6）的栅极 - 漏极电压等于晶体管（5）的基极 - 发射极电压。因此，晶体管（6）工作在五极管区域，用作晶体管（5）的恒定电流负载。

5. 发明授权

US5313207A Differential subtracter improved for higher accuracy and A/D converter including the same 失效
标题翻译：对于较高精度的差分减法器和包括相同的A / D转换器
公开(公告)号：US5313207A
公开(公告)日：1994-05-17
申请号：US71497
申请日：1993-06-04
申请人： Hiroyuki Kouno , Takahiro Miki , Toshio Kumamoto
发明人： Hiroyuki Kouno , Takahiro Miki , Toshio Kumamoto
IPC分类号： H03F3/45 , G06G7/14 , H03F3/72 , H03M1/14 , H03M1/34 , H03M1/36 , H03M1/12
CPC分类号： H03M1/164 , G06G7/14 , H03F3/72
摘要： An improved differential subtracter 3a and an improved D/A converter 7a are used in a two-step parallel A/D converter 100. The D/A converter is responsive to complementary signals S1-S2 and B1-Bn indicative of results of conversion of higher bits to draw subtraction currents Is1 and Is2 through emitter electrodes of npn transistors Q1 and Q2. Since a difference between emitter currents I.sub.E1 and I.sub.E2 is small, base-emitter voltages V.sub.BE1 and V.sub.BE2 are substantially equal to each other. As a result, the A/D converter can execute the subtraction at high speed with high accuracy.
摘要翻译：改进的差分减法器3a和改进的D / A转换器7a用于两级并行A / D转换器100.D / A转换器响应于指示转换结果的互补信号S1-S2和B1-Bn 较高位以通过npn晶体管Q1和Q2的发射极来减去电流Is1和Is2。由于发射极电流IE1和IE2之间的差异小，所以基极 - 发射极电压VBE1和VBE2基本相等。因此，A / D转换器可以高精度地执行减法。

6. 发明授权

US06522007B2 Semiconductor device having dummy patterns for metal CMP 失效
标题翻译：具有用于金属CMP的虚设图案的半导体器件
公开(公告)号：US06522007B2
公开(公告)日：2003-02-18
申请号：US09974856
申请日：2001-10-12
申请人： Hiroyuki Kouno , Toshio Kumamoto , Takahiro Miki , Hisayasu Satoh
发明人： Hiroyuki Kouno , Toshio Kumamoto , Takahiro Miki , Hisayasu Satoh
IPC分类号： H01L2348
CPC分类号： H01L27/08 , H01L21/31053 , H01L21/76819 , H01L21/76838 , H01L21/823437 , H01L23/5227 , H01L23/528 , H01L29/42372 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A gate electrode has a relatively long gate length of e.g., about 10 &mgr;m. In a region immediately above the gate electrode which is sandwiched between first-layer metals provided is a metal dummy pattern having a width in the first direction and extending in the second direction perpendicular to a direction of gate length (direction of current flow). Moreover, a geometric center of the metal dummy pattern in the second direction is equal to a geometric center of the gate electrode in the second direction. This maintains the symmetry in shape of the metal dummy pattern as viewed from the gate electrode. Such a structure can make deterioration in characteristics of a plurality of elements uniform while maintaining the essential effect of a metal CMP.
摘要翻译：栅电极具有例如约10μm的较长栅极长度。在夹在所提供的第一层金属之间的栅电极正上方的区域是具有第一方向的宽度并且沿与栅极长度方向（电流方向）垂直的第二方向延伸的金属虚设图案。此外，第二方向上的金属虚设图案的几何中心等于栅电极在第二方向上的几何中心。这保持了从栅电极观察时的金属虚设图形的对称性。这样的结构可以使多个元件的特性劣化，同时保持金属CMP的基本效果。

7. 发明授权

US5345237A Differential amplifier and two-step parallel A/D converter 失效
标题翻译：差分放大器和两级并行A / D转换器
公开(公告)号：US5345237A
公开(公告)日：1994-09-06
申请号：US77932
申请日：1993-06-18
申请人： Hiroyuki Kouno , Takahiro Miki , Toshio Kumamoto
发明人： Hiroyuki Kouno , Takahiro Miki , Toshio Kumamoto
IPC分类号： H03F3/45 , H03M1/14 , H03M1/36 , H03M1/34
CPC分类号： H03M1/146 , H03F3/45071 , H03M1/365
摘要： The present invention is directed to improvement of a differential amplifier an its peripheral components employed in an A/D converter to enhance an accuracy of the A/D converter. The differential amplifier has an amplifying element comprised of a pair of differential transistors Q1 and Q2, emitter resistances 2a and 2b, and collector resistances 2c and 2d. The differential amplifier has transistors Q3 and Q4 constituting an emitter follower for applying an output amplified in the differential amplifying element to the outside. The differential amplifier includes transistors Q5 and Q6 having their respective base electrodes connected to input terminals 4a and 4b and serially connected to the transistors Q3 and Q4, and resistances 2e and 2f interposed between emitter electrodes of the transistors Q5 and Q6 so as to relieve any influence of variations in base-emitter voltages of the transistors Q3 and Q4. Effectively an output from the emitter follower can be improved and a gain of the differential amplifier and linearity can be also improved.
摘要翻译：本发明旨在改进差分放大器及其在A / D转换器中采用的周边部件，以提高A / D转换器的精度。差分放大器具有由一对差分晶体管Q1和Q2，发射极电阻2a和2b以及集电极电阻2c和2d组成的放大元件。差分放大器具有构成射极跟随器的晶体管Q3和Q4，用于将在差分放大元件中放大的输出施加到外部。差分放大器包括具有连接到输入端子4a和4b并且串联连接到晶体管Q3和Q4的各自的基极的晶体管Q5和Q6，以及夹在晶体管Q5和Q6的发射极之间的电阻2e和2f，以便减轻任何晶体管Q3和Q4的基极 - 发射极电压变化的影响。有效地提高了射极跟随器的输出，并且还可以提高差分放大器的增益和线性度。

8. 发明授权

US5539406A Series-parallel type A-D converter for realizing high speed operation and low power consumption 失效
标题翻译：串并联型A-D转换器，实现高速运行和低功耗
公开(公告)号：US5539406A
公开(公告)日：1996-07-23
申请号：US264676
申请日：1994-06-23
申请人： Hiroyuki Kouno , Toshio Kumamoto , Takahiro Miki
发明人： Hiroyuki Kouno , Toshio Kumamoto , Takahiro Miki
IPC分类号： H03M1/06 , H03M1/14 , H03M1/36 , H03M1/76 , H03M1/12
CPC分类号： H03M1/146 , H03M1/0682 , H03M1/365 , H03M1/765
摘要： An upper comparator group compares an analog signal with upper reference potentials applied from upper ladder resistance network. A switch group outputs the predetermined intermediate reference potential of the ladder resistance network to an analog subtracting circuit in response to the upper comparison results. The analog subtracting circuit subtracts the intermediate reference potential from the analog signal for producing an input signal for use in the lower side. A lower ladder resistance network outputs lower reference potentials obtained by dividing by resistors constant static intermediate reference potentials of the ladder resistance network applied from a differential amplifying circuit. A lower comparator group compares the lower reference potentials with the input signal for lower comparison. The upper and the lower comparison results are converted into a digital signal by upper and the lower encoders and the adding/subtracting circuit.
摘要翻译：上比较器组将模拟信号与上梯形电阻网络施加的较高参考电位进行比较。开关组响应于较高的比较结果将梯形电阻网络的预定中间参考电位输出到模拟减法电路。模拟减法电路从用于产生用于下侧的输入信号的模拟信号中减去中间参考电位。下梯形电阻网络通过将电阻除以由差分放大电路施加的梯形电阻网络的恒定静态中间参考电位而得到的较低参考电位。较低的比较器组将较低的参考电位与输入信号进行比较，用于较低的比较。上下比较结果由上下编码器和加减电路转换成数字信号。

9. 发明授权

US5196920A Semiconductor integrated circuit device for limiting capacitive coupling between adjacent circuit blocks 失效
标题翻译：用于限制相邻电路块之间的电容耦合的半导体集成电路器件
公开(公告)号：US5196920A
公开(公告)日：1993-03-23
申请号：US871655
申请日：1992-04-21
申请人： Toshio Kumamoto , Hiroyuki Kouno
发明人： Toshio Kumamoto , Hiroyuki Kouno
IPC分类号： H01L23/552 , H01L23/58 , H01L25/065 , H01L25/18 , H01L27/02 , H01L27/06
CPC分类号： H01L23/552 , H01L23/585 , H01L25/0657 , H01L25/18 , H01L27/0688 , H01L2225/06541 , H01L27/0203 , H01L2924/0002
摘要： A semiconductor integrated circuit device having semiconductor integrated circuit blocks disposed close to each other. An insulating layer is interposed between each adjacent pair of the semiconductor integrated circuit blocks. An electroconductive shield member is formed between the adjacent semiconductor integrated circuit blocks to limit the capacitive coupling therebetween. The shield member is electrically insulated from the semiconductor integrated circuit blocks and is maintained at a predetermined fixed potential.
摘要翻译：具有彼此靠近设置的半导体集成电路块的半导体集成电路器件。在每个相邻的一对半导体集成电路块之间插入绝缘层。在相邻的半导体集成电路块之间形成导电屏蔽部件，以限制它们之间的电容耦合。屏蔽构件与半导体集成电路块电绝缘并保持在预定的固定电位。

10. 发明授权

US5041884A Multilayer semiconductor integrated circuit 失效
标题翻译：多层半导体集成电路
公开(公告)号：US5041884A
公开(公告)日：1991-08-20
申请号：US596069
申请日：1990-10-11
申请人： Toshio Kumamoto , Hiroyuki Kouno
发明人： Toshio Kumamoto , Hiroyuki Kouno
IPC分类号： H01L27/06 , H01L29/786
CPC分类号： H01L27/0688 , H01L29/78642 , H01L29/78648 , H01L2924/0002
摘要： The inventive multilayer semiconductor integrated circuit has a columnar semiconductor region provided between adjacent two layers and a control electrode provided in the vicinity of the columnar semiconductor region. The transference of a signal between the adjacent two layers is carried out through the columnar semiconductor region the electric conductivity of which is controlled by a control signal applied to the control electrode. That is, the area corresponding to the columnar semiconductor region functions as an active element.
摘要翻译：本发明的多层半导体集成电路具有设置在相邻的两层之间的柱状半导体区域和设置在柱状半导体区域附近的控制电极。通过施加到控制电极的控制信号控制其电导率的柱状半导体区域，进行相邻两层之间的信号的转移。也就是说，对应于柱状半导体区域的区域用作有源元件。

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