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    • 1. 发明授权
    • Endoscope apparatus
    • 内窥镜装置
    • US06572537B2
    • 2003-06-03
    • US09769073
    • 2001-01-25
    • Yasuyuki FutatsugiHidetoshi SaitoYosuke YoshimotoSusumu AonoSatoshi HonmaHitoshi Karasawa
    • Yasuyuki FutatsugiHidetoshi SaitoYosuke YoshimotoSusumu AonoSatoshi HonmaHitoshi Karasawa
    • A61B100
    • A61B1/05
    • An endoscope includes an image pickup unit 30 having a solid-state image pickup device 32 such as a CCD on a tip end side of an elongate insertion section. This image pickup unit 30 constitutes a tip end side unit 36U and a rear end side unit 43U by conducting a surface treatment (metallization) to nonmetal members such as a tip end cover glass 31 and a rear end cover glass 35, and by airtight coupling surface-treated portions of the nonmetal members to metal members such as a tip end cover glass frame 36 and a rear end cover glass frame 43 by brazing using soldering, and constitutes an optical system unit 60 by airtight coupling the metal members to metal members of an insulating unit 38U formed by airtight coupling a pipe member 41 and a ring member 42 to an insulating frame 38 by welding.
    • 内窥镜包括在细长插入部的前端侧具有像CCD这样的固体摄像装置32的摄像单元30。 该图像拾取单元30通过对诸如前端盖玻璃31和后端盖玻璃35的非金属构件进行表面处理(金属化)而形成前端侧单元36U和后端侧单元43U,并且通过气密耦合 通过钎焊钎焊将非金属构件的表面处理部分的前端盖玻璃框架36和后端盖玻璃框架43的金属构件表面处理,并且通过将金属构件气密地连接到金属构件的金属构件 通过焊接将管构件41和环构件42气密地连接到绝缘框架38而形成的绝缘单元38U。
    • 8. 发明授权
    • Semiconductor integrated circuit device
    • 半导体集成电路器件
    • US07382670B2
    • 2008-06-03
    • US11669420
    • 2007-01-31
    • Tomohito KawanoHidetoshi Saito
    • Tomohito KawanoHidetoshi Saito
    • G11C7/00
    • G11C29/34G11C16/04G11C2029/1204G11C2029/1802G11C2029/2602
    • There is disclosed a semiconductor integrated circuit device having first and second load circuits for write. At the time of an all bit-stress test, a high voltage for write is supplied from the first and second load circuits for write to the all bit lines. At the time of an even bit-stress test, the high voltage for write is supplied from the first load circuit for write to the even bit lines and a lower potential than the high voltage for write is supplied from the second load circuit for write to the odd bit lines. At the time of an odd bit-stress test, the lower potential is supplied from the first load circuit for write to the even bit lines and the high voltage for write is supplied from the second load circuit for write to the odd bit lines.
    • 公开了一种具有用于写入的第一和第二负载电路的半导体集成电路器件。 在所有位应力测试时,从第一和第二负载电路提供用于写入的高电压用于写入所有位线。 在进行偶数位应力测试时,写入的高电压从第一负载电路提供给偶数位线,并且比写入的高电压低的电位从第二负载电路提供给写入 奇数位线。 在奇数位应力测试时,较低的电位从第一负载电路提供给偶数位线,并且用于写入的高电压从第二负载电路提供给奇数位线。
    • 9. 发明授权
    • Semiconductor memory device
    • 半导体存储器件
    • US06906960B2
    • 2005-06-14
    • US10383633
    • 2003-03-10
    • Hidetoshi SaitoHideo KatoTokumasa Hara
    • Hidetoshi SaitoHideo KatoTokumasa Hara
    • G11C16/02G11C8/12G11C16/08G11C16/04
    • G11C8/12G11C16/08G11C2216/22
    • A semiconductor memory device includes: a plurality of banks with electrically rewritable memory cells arranged therein, the banks being configured to be simultaneously accessible in such a manner that a data write operation into a bank and a data read operation for another bank are simultaneously performed; a write-use data bus commonly disposed for the plurality of banks; a read-use data bus commonly disposed for the plurality of banks; a write circuit connected to the write-use data bus; a read circuit connected to the read-use data bus; a bank address decoder circuit for decoding external bank address signals for bank selecting to output internal bank address signals, the bank address decoder circuit having such an address conversion function that one of plural kinds of address conversions between the external bank address signals and the internal bank address signals is selectable; and a rewrite control circuit for sequence controlling a data write operation for a bank selected by the bank address decoder circuit.
    • 一种半导体存储器件包括:具有布置在其中的电可重写存储器单元的多个存储体,所述存储体被配置为可同时访问,以使得对于存储体的数据写操作和对于另一存储体的数据读操作同时进行; 通常为多个银行设置的写用数据总线; 通常为多个银行设置的读取用数据总线; 连接到写入用数据总线的写入电路; 连接到读取用数据总线的读取电路; 用于解码用于存储体选择的外部存储体地址信号以输出内部存储体地址信号的存储体地址解码器电路,该存储体地址译码器电路具有这样一种地址转换功能:外部存储体地址信号与内部存储体之间的多种地址转换之一 地址信号可选; 以及重写控制电路,用于对由银行地址解码器电路选择的存储体进行数据写入操作的顺序控制。