专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20120223376A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120223376A1
公开(公告)日：2012-09-06
申请号：US13469266
申请日：2012-05-11
申请人： Kazuyoshi Shiba , Yasushi Oka
发明人： Kazuyoshi Shiba , Yasushi Oka
IPC分类号： H01L27/108
CPC分类号： H01L27/11558 , G11C16/0441 , H01L27/0207 , H01L27/0629 , H01L27/105 , H01L27/11519 , H01L27/11521 , H01L27/11526
摘要： p-type wells are provided within an n-type embedded well of a semiconductor substrate lying in an area for forming a flash memory, in a state of being isolated from one another. A capacitance section, a data write/erase charge injection/discharge section and a data read MIS•FET are disposed in each of the p-type wells. The capacitance section is disposed between the data write/erase charge injection/discharge section and the data read MIS•FET. In the data write/erase charge injection/discharge section, writing and erasing of data by an FN tunnel current at a channel entire surface are performed.
摘要翻译： p型阱设置在位于形成闪存的区域中的半导体衬底的n型嵌入阱中，处于彼此隔离的状态。电容部分，数据写入/擦除电荷注入/放电部分和数据读取MIS·FET被设置在每个p型阱中。电容部分设置在数据写入/擦除电荷注入/放电部分和数据读取MIS•FET之间。在数据写入/擦除电荷注入/放电部分中，执行通道整个表面处的FN隧道电流的数据写入和擦除。

2. 发明授权

US07639541B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07639541B2
公开(公告)日：2009-12-29
申请号：US11971546
申请日：2008-01-09
申请人： Kazuyoshi Shiba , Yasushi Oka
发明人： Kazuyoshi Shiba , Yasushi Oka
IPC分类号： G11C11/03
CPC分类号： H01L27/115 , G11C16/0441 , G11C2216/26 , H01L27/11521 , H01L27/11558
摘要： A semiconductor device includes a circuit forming area and a memory area including memory cells, first and second wells, a first conductor film formed over both wells and a second conductor film formed over the first well. First semiconductor regions are formed in the first region and a second semiconductor region is formed in the second region. The memory cells each include a capacitance element, including the first conductor film and second region, an element for reading data, including the first conductor film and first regions, and a selection field effect transistor, including the second conductor film and first regions. A length of the first conductor film of the capacitance element is larger than a length of the first conductor film of the element for reading data. A word line of the memory cell is connected to the second semiconductor region. During a reading data operation, a first bit line of the memory cell is connected to the first semiconductor region of the element for reading data via the selection field effect transistor.
摘要翻译：半导体器件包括电路形成区域和包括存储单元，第一和第二阱，形成在两个阱上的第一导体膜和形成在第一阱上的第二导体膜的存储区域。第一半导体区域形成在第一区域中，并且在第二区域中形成第二半导体区域。存储单元各自包括包括第一导体膜和第二区域的电容元件，包括第一导体膜和第一区域的用于读取数据的元件，以及包括第二导体膜和第一区域的选择场效应晶体管。电容元件的第一导体膜的长度大于用于读取数据的元件的第一导体膜的长度。存储单元的字线连接到第二半导体区域。在读取数据操作期间，存储单元的第一位线连接到用于经由选择场效应晶体管读取数据的元件的第一半导体区域。

3. 发明授权

US07652917B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07652917B2
公开(公告)日：2010-01-26
申请号：US12260124
申请日：2008-10-29
申请人： Yasushi Oka , Kazuyoshi Shiba
发明人： Yasushi Oka , Kazuyoshi Shiba
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： H01L27/115 , G11C16/0433 , H01L27/11521 , H01L27/11558
摘要： In a data program/erase device of a nonvolatile memory cell, data are re-written by means of an FN tunnel current of an entire channel surface. In a buried n-well of a semiconductor substrate in a flash memory formation region, p wells are placed in the form isolated from each other. In each of the p wells, a capacitor portion, a capacitor portion for programming/erasing data and an MIS•FET for reading data are placed. In the capacitor portion for programming/erasing data, rewriting (programming and erasing) of data is performed by means of an FN tunnel current of an entire channel surface.
摘要翻译：在非易失性存储单元的数据编程/擦除装置中，通过整个通道表面的FN隧道电流重写数据。在闪速存储器形成区域中的半导体衬底的掩埋n阱中，p阱以彼此分离的形式放置。在每个p阱中，放置电容器部分，用于编程/擦除数据的电容器部分和用于读取数据的MIS.FET。在用于编程/擦除数据的电容器部分中，通过整个通道表面的FN隧道电流来执行数据的重写（编程和擦除）。

4. 发明申请

US20080211001A1 SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080211001A1
公开(公告)日：2008-09-04
申请号：US12013470
申请日：2008-01-13
申请人： Kazuyoshi Shiba , Hideyuki Yashima , Yasushi Oka
发明人： Kazuyoshi Shiba , Hideyuki Yashima , Yasushi Oka
IPC分类号： H01L27/06 , H01L21/28
CPC分类号： H01L27/105 , H01L27/1052 , H01L27/11526 , H01L27/11529 , H01L29/7833
摘要： Provided is a semiconductor device having, over the main surface of a semiconductor substrate, a main circuit region and a memory cell array of a flash memory. The memory cell array has a floating gate electrode for accumulating charges of data, while the main circuit region has a gate electrode of MIS•FET constituting the main circuit. In the main circuit region, an insulating film made of a silicon nitride film is formed to cover the gate electrode, whereby miniaturization of elements in the main circuit region is not impaired. The memory cell array has no such insulating film. This means that the upper surface of the floating gate electrode is not contiguous to the insulating film but is covered directly with an interlayer insulating film. According to such a constitution, leakage of electrons from the floating gate electrode of the memory cell array can be suppressed or prevented and the flash memory thus obtained has improved data retention characteristics.
摘要翻译：提供一种半导体器件，其在半导体衬底的主表面上具有闪存的主电路区域和存储单元阵列。存储单元阵列具有用于累积数据电荷的浮栅电极，而主电路区域具有构成主电路的MIS.FET的栅电极。在主电路区域中，形成由氮化硅膜构成的绝缘膜，以覆盖栅电极，从而不损害主电路区域中元件的小型化。存储单元阵列不具有这种绝缘膜。这意味着浮栅电极的上表面不与绝缘膜邻接，而是直接用层间绝缘膜覆盖。根据这种结构，可以抑制或防止电子从存储单元阵列的浮置栅电极泄漏，从而获得的闪速存储器具有改善的数据保持特性。

5. 发明授权

US07623371B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07623371B2
公开(公告)日：2009-11-24
申请号：US11743515
申请日：2007-05-02
申请人： Kazuyoshi Shiba , Yasushi Oka
发明人： Kazuyoshi Shiba , Yasushi Oka
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： H01L27/11558 , G11C16/0441 , H01L27/0207 , H01L27/0629 , H01L27/105 , H01L27/11519 , H01L27/11521 , H01L27/11526
摘要： p-type wells are provided within an n-type embedded well of a semiconductor substrate lying in an area for forming a flash memory, in a state of being isolated from one another. A capacitance section, a data write/erase charge injection/discharge section and a data read MIS•FET are disposed in each of the p-type wells. The capacitance section is disposed between the data write/erase charge injection/discharge section and the data read MIS•FET. In the data write/erase charge injection/discharge section, writing and erasing of data by an FN tunnel current at a channel entire surface are performed.
摘要翻译： p型阱设置在位于形成闪存的区域中的半导体衬底的n型嵌入阱中，处于彼此隔离的状态。在每个p型阱中设置电容部分，数据写/擦除电荷注入/放电部分和数据读取MIS.FET。电容部分设置在数据写入/擦除电荷注入/放电部分和读取的MIS.FET数据之间。在数据写入/擦除电荷注入/放电部分中，执行通道整个表面处的FN隧道电流的数据写入和擦除。

6. 发明授权

US07466599B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07466599B2
公开(公告)日：2008-12-16
申请号：US11925106
申请日：2007-10-26
申请人： Kazuyoshi Shiba , Yasuhiro Taniguchi , Yasushi Oka
发明人： Kazuyoshi Shiba , Yasuhiro Taniguchi , Yasushi Oka
IPC分类号： G11C16/04
CPC分类号： G11C16/0408 , G11C2216/10 , H01L27/112
摘要： Provided is a nonvolatile memory with less element deterioration and good data retaining properties. In a nonvolatile memory formed by the manufacturing steps of a complementary type MISFET without adding thereto another additional step, erasing of data is carried out by applying 9V to an n type well, 9V to a p type semiconductor region, and −9V to another p type semiconductor region and setting the source and drain of data writing and erasing MISFETs and data reading MISFETs at open potential to emit electrons from a gate electrode to a p well by FN tunneling. At this time, by applying a negative voltage to the p well having a capacitive element formed thereover and applying a positive voltage to the p well having the MISFETs formed thereover, a potential difference necessary for data erasing operation can be secured at a voltage low enough not to cause gate breakage.
摘要翻译：提供了具有较少元件劣化和良好的数据保存性能的非易失性存储器。在通过互补型MISFET的制造步骤形成的非易失性存储器中，而不添加另外的附加步骤，通过将9V施加到n型阱，9V到ap型半导体区域，并将-9V施加到另一个p型，进行数据擦除半导体区域，并设置数据写入和擦除MISFET和数据读取MISFET的源极和漏极，其处于开放电位，以通过FN隧穿从栅电极发射电子。此时，通过向其中形成有电容元件的p阱施加负电压并向其上形成有MISFET的p阱施加正电压，可以在足够低的电压下确保数据擦除操作所需的电位差不会造成门破损。

7. 发明申请

US20080056011A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20080056011A1
公开(公告)日：2008-03-06
申请号：US11925106
申请日：2007-10-26
申请人： Kazuyoshi Shiba , Yasuhiro Taniguchi , Yasushi Oka
发明人： Kazuyoshi Shiba , Yasuhiro Taniguchi , Yasushi Oka
IPC分类号： G11C11/34 , H01L21/31
CPC分类号： G11C16/0408 , G11C2216/10 , H01L27/112
摘要： Provided is a nonvolatile memory with less element deterioration and good data retaining properties. In a nonvolatile memory formed by the manufacturing steps of a complementary type MISFET without adding thereto another additional step, erasing of data is carried out by applying 9V to an n type well, 9V to a p type semiconductor region, and −9V to another p type semiconductor region and setting the source and drain of data writing and erasing MISFETs and data reading MISFETs at open potential to emit electrons from a gate electrode to a p well by FN tunneling. At this time, by applying a negative voltage to the p well having a capacitive element formed thereover and applying a positive voltage to the p well having the MISFETs formed thereover, a potential difference necessary for data erasing operation can be secured at a voltage low enough not to cause gate breakage.
摘要翻译：提供了具有较少元件劣化和良好的数据保存性能的非易失性存储器。在通过互补型MISFET的制造步骤形成的非易失性存储器中，而不添加另外的附加步骤，通过将9V施加到n型阱，9V到ap型半导体区域，并将-9V施加到另一个p型来进行数据擦除半导体区域，并设置数据写入和擦除MISFET和数据读取MISFET的源极和漏极，其处于开放电位，以通过FN隧穿从栅电极发射电子。此时，通过向其中形成有电容元件的p阱施加负电压并向其上形成有MISFET的p阱施加正电压，可以在足够低的电压下确保数据擦除操作所需的电位差不会造成门破损。

8. 发明申请

US20070296020A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20070296020A1
公开(公告)日：2007-12-27
申请号：US11743515
申请日：2007-05-02
申请人： Kazuyoshi SHIBA , Yasushi Oka
发明人： Kazuyoshi SHIBA , Yasushi Oka
IPC分类号： H01L29/788
CPC分类号： H01L27/11558 , G11C16/0441 , H01L27/0207 , H01L27/0629 , H01L27/105 , H01L27/11519 , H01L27/11521 , H01L27/11526
摘要： p-type wells are provided within an n-type embedded well of a semiconductor substrate lying in an area for forming a flash memory, in a state of being isolated from one another. A capacitance section, a data write/erase charge injection/discharge section and a data read MIS•FET are disposed in each of the p-type wells. The capacitance section is disposed between the data write/erase charge injection/discharge section and the data read MIS•FET. In the data write/erase charge injection/discharge section, writing and erasing of data by an FN tunnel current at a channel entire surface are performed.
摘要翻译： p型阱设置在位于形成闪存的区域中的半导体衬底的n型嵌入阱中，处于彼此隔离的状态。在每个p型阱中设置电容部分，数据写/擦除电荷注入/放电部分和数据读取MIS.FET。电容部分设置在数据写入/擦除电荷注入/放电部分和读取的MIS.FET数据之间。在数据写入/擦除电荷注入/放电部分中，执行通道整个表面处的FN隧道电流的数据写入和擦除。

9. 发明申请

US20060050566A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20060050566A1
公开(公告)日：2006-03-09
申请号：US11206968
申请日：2005-08-19
申请人： Kazuyoshi Shiba , Yasuhiro Taniguchi , Yasushi Oka
发明人： Kazuyoshi Shiba , Yasuhiro Taniguchi , Yasushi Oka
IPC分类号： G11C16/04
CPC分类号： G11C16/0408 , G11C2216/10 , H01L27/112
摘要： Provided is a nonvolatile memory with less element deterioration and good data retaining properties. In a nonvolatile memory formed by the manufacturing steps of a complementary type MISFET without adding thereto another additional step, erasing of data is carried out by applying 9V to an n type well, 9V to a p type semiconductor region, and −9V to another p type semiconductor region and setting the source and drain of data writing and erasing MISFETs and data reading MISFETs at open potential to emit electrons from a gate electrode to a p well by FN tunneling. At this time, by applying a negative voltage to the p well having a capacitive element formed thereover and applying a positive voltage to the p well having the MISFETs formed thereover, a potential difference necessary for data erasing operation can be secured at a voltage low enough not to cause gate breakage.
摘要翻译：提供了具有较少元件劣化和良好的数据保存性能的非易失性存储器。在通过互补型MISFET的制造步骤形成的非易失性存储器中，而不添加另外的附加步骤，通过将9V施加到n型阱，9V到ap型半导体区域，并将-9V施加到另一个p型来进行数据擦除半导体区域，并设置数据写入和擦除MISFET和数据读取MISFET的源极和漏极，其处于开放电位，以通过FN隧穿从栅电极发射电子。此时，通过向其中形成有电容元件的p阱施加负电压并向其上形成有MISFET的p阱施加正电压，可以在足够低的电压下确保数据擦除操作所需的电位差不会造成门破损。

10. 发明授权

US08351255B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08351255B2
公开(公告)日：2013-01-08
申请号：US13469266
申请日：2012-05-11
申请人： Kazuyoshi Shiba , Yasushi Oka
发明人： Kazuyoshi Shiba , Yasushi Oka
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： H01L27/11558 , G11C16/0441 , H01L27/0207 , H01L27/0629 , H01L27/105 , H01L27/11519 , H01L27/11521 , H01L27/11526
摘要： p-type wells are provided within an n-type embedded well of a semiconductor substrate lying in an area for forming a flash memory, in a state of being isolated from one another. A capacitance section, a data write/erase charge injection/discharge section and a data read MIS•FET are disposed in each of the p-type wells. The capacitance section is disposed between the data write/erase charge injection/discharge section and the data read MIS•FET. In the data write/erase charge injection/discharge section, writing and erasing of data by an FN tunnel current at a channel entire surface are performed.
摘要翻译： p型阱设置在位于形成闪存的区域中的半导体衬底的n型嵌入阱中，处于彼此隔离的状态。电容部分，数据写入/擦除电荷注入/放电部分和数据读取MIS·FET被设置在每个p型阱中。电容部分设置在数据写入/擦除电荷注入/放电部分和数据读取MIS•FET之间。在数据写入/擦除电荷注入/放电部分中，执行通道整个表面处的FN隧道电流的数据写入和擦除。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式