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1. 发明授权

US07859938B2 Semiconductor memory device and test method thereof 有权
标题翻译：半导体存储器件及其测试方法
公开(公告)号：US07859938B2
公开(公告)日：2010-12-28
申请号：US12233278
申请日：2008-09-18
申请人： Yasushi Matsubara
发明人： Yasushi Matsubara
IPC分类号： G11C8/00
CPC分类号： G11C29/02 , G11C29/006 , G11C29/021 , G11C29/028
摘要： When a predetermined code is set to a mode register, a switching signal generating circuit is activated, and a switching signal TCLKE becomes at a high level. When the switching signal TCLKE becomes at a high level, input data supplied from a data input and output terminal DQ is used as an internal clock ICLK. Accordingly, during a test in a wafer state, a clock signal can be received from the data input and output terminal DQ, even when a clock terminal, an address terminal, and a command terminal are connected in common to plural semiconductor memory devices. Therefore, a code for artificially performing a fine adjustment of a reference voltage can be individually supplied for each chip.
摘要翻译：当将预定代码设置为模式寄存器时，切换信号发生电路被激活，并且切换信号TCLKE变为高电平。当切换信号TCLKE变为高电平时，从数据输入和输出端DQ提供的输入数据用作内部时钟ICLK。因此，即使在将时钟端子，地址端子和指令端子共同连接到多个半导体存储器件时，在晶片状态的测试中也可以从数据输入和输出端子DQ接收时钟信号。因此，可以对每个芯片分别提供用于人为地进行参考电压的微调的代码。

2. 发明授权

US07751998B2 Semiconductor device, method for measuring characteristics of element to be measured, and characteristic management system of semiconductor device 有权
标题翻译：半导体装置，测量元件的特性的测量方法以及半导体器件的特性管理系统
公开(公告)号：US07751998B2
公开(公告)日：2010-07-06
申请号：US11898551
申请日：2007-09-13
申请人： Yasushi Matsubara
发明人： Yasushi Matsubara
IPC分类号： G01N37/00
CPC分类号： G01R31/31721 , G11C29/02 , G11C29/12005 , G11C29/50 , G11C2029/5006
摘要： A plurality of series circuits each consisting of a current-carrying element and an element to be measured are provided between a power supply potential VDD and a ground potential VSS. The current-carrying elements are supplied with a test signal commonly, and corresponding selection signals, respectively. After a mode is set so that power consumption of a main circuit unit included in a semiconductor device is substantially zero or almost constant, the elements to be measured are energized sequentially and, in this state, a power supply current that flows through the semiconductor device is measured sequentially. Accordingly, it is possible to accurately know the power consumption of the element to be measured and it is also possible to know the characteristics of the element to be measured based thereon.
摘要翻译：在电源电位VDD和接地电位VSS之间设置多个串联电路，每个串联电路由载流元件和待测元件构成。载流元件分别被提供有一个测试信号和相应的选择信号。在设置模式之后，使得包括在半导体器件中的主电路单元的功耗基本为零或几乎恒定，所测量的元件依次通电，并且在该状态下，流过半导体器件的电源电流依次测量。因此，可以准确地知道要测量的元件的功耗，并且也可以基于此来知道要测量的元件的特性。

3. 发明申请

US20100156500A1 SEMICONDUCTOR DEVICE, OUTPUT CIRCUIT AND METHOD FOR CONTROLLING INPUT/OUTPUT BUFFER CIRCUIT IN SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件，输出电路和用于控制半导体器件中的输入/输出缓冲器电路的方法
公开(公告)号：US20100156500A1
公开(公告)日：2010-06-24
申请号：US12644956
申请日：2009-12-22
申请人： Yasushi Matsubara , Minari Arai
发明人： Yasushi Matsubara , Minari Arai
IPC分类号： H03L5/00
CPC分类号： H03K19/018585 , G11C7/1051 , G11C7/1057 , H03K19/018507
摘要： Disclosed is a semiconductor device having an output circuit that may be used to advantage in case the semiconductor device may possibly be used under different power supply voltages. The semiconductor device includes a signal terminal having at least the function of an output terminal, a power supply terminal, and an output circuit having first and second output buffer circuits. The first and second output buffer circuits are supplied with a supply power voltage from the power supply terminal and receive an inner output signal to drive the signal terminal. The semiconductor device also includes a power supply voltage discrimination circuit that discriminates the potential level of the power supply voltage to control the operation of the output circuit based on the result of discrimination. A first output buffer circuit is activated and a second output buffer circuit is deactivated in case the power supply voltage discrimination circuit has decided that the power supply voltage is at a first potential. Both of the first and second output buffer circuits are activated in case the power supply voltage discrimination circuit has decided that the power supply voltage is at a second potential.
摘要翻译：公开了具有输出电路的半导体器件，其可以在半导体器件可能在不同的电源电压下使用的情况下被使用。半导体器件包括至少具有输出端子，电源端子和具有第一和第二输出缓冲器电路的输出电路的功能的信号端子。向第一和第二输出缓冲器电路提供来自电源端的电源电压，并接收内部输出信号以驱动信号端子。半导体器件还包括电源电压鉴别电路，其基于鉴别结果来鉴别电源电压的电位电平以控制输出电路的操作。在电源电压鉴别电路已经确定电源电压处于第一电位的情况下，第一输出缓冲电路被激活并且第二输出缓冲电路被去激活。在电源电压鉴别电路已经确定电源电压处于第二电位的情况下，第一和第二输出缓冲电路都被激活。

4. 发明申请

US20080068037A1 Semiconductor device, method for measuring characteristics of element to be measured, and characteristic management system of semiconductor device 有权
标题翻译：半导体装置，测量元件的特性的测量方法以及半导体器件的特性管理系统
公开(公告)号：US20080068037A1
公开(公告)日：2008-03-20
申请号：US11898551
申请日：2007-09-13
申请人： Yasushi Matsubara
发明人： Yasushi Matsubara
IPC分类号： G01R31/26 , H01L23/58
CPC分类号： G01R31/31721 , G11C29/02 , G11C29/12005 , G11C29/50 , G11C2029/5006
摘要： A plurality of series circuits each consisting of a current-carrying element and an element to be measured are provided between a power supply potential VDD and a ground potential VSS. The current-carrying elements are supplied with a test signal commonly, and corresponding selection signals, respectively. After a mode is set so that power consumption of a main circuit unit included in a semiconductor device is substantially zero or almost constant, the elements to be measured are energized sequentially and, in this state, a power supply current that flows through the semiconductor device is measured sequentially. Accordingly, it is possible to accurately know the power consumption of the element to be measured and it is also possible to know the characteristics of the element to be measured based thereon.
摘要翻译：在电源电位VDD和接地电位VSS之间设置多个串联电路，每个串联电路由载流元件和待测元件构成。载流元件分别被提供有一个测试信号和相应的选择信号。在设置模式之后，使得包括在半导体器件中的主电路单元的功耗基本为零或几乎恒定，所测量的元件依次通电，并且在该状态下，流过半导体器件的电源电流依次测量。因此，可以准确地知道要测量的元件的功耗，并且也可以基于此来知道要测量的元件的特性。

5. 发明申请

US20060140029A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20060140029A1
公开(公告)日：2006-06-29
申请号：US11315698
申请日：2005-12-22
申请人： Yasushi Matsubara
发明人： Yasushi Matsubara
IPC分类号： G11C29/00
CPC分类号： G11C29/842
摘要： A redundancy replacement judging circuit includes a redundancy replacement judging circuit chain and a pseudo redundancy replacement judging circuit chain substantially equal in delay time to the redundancy replacement judging circuit chain. In response to an output of the pseudo redundancy replacement judging circuit chain, the redundancy replacement judging circuit outputs a redundancy judgment result of the redundancy replacement judging circuit chain. A semiconductor memory device includes the redundancy replacement judging circuit.
摘要翻译：冗余替换判断电路包括冗余替换判断电路链和在冗余替换判断电路链上延迟时间基本相等的伪冗余替换判断电路链。响应于伪冗余替换判断电路链的输出，冗余替换判断电路输出冗余替换判断电路链的冗余判断结果。半导体存储器件包括冗余替换判断电路。

6. 发明授权

US07463529B2 Word line driving circuit putting word line into one of high level, low level and high impedance 有权
标题翻译：字线驱动电路将字线置于高电平，低电平和高阻抗之一
公开(公告)号：US07463529B2
公开(公告)日：2008-12-09
申请号：US11723609
申请日：2007-03-21
申请人： Yasushi Matsubara
发明人： Yasushi Matsubara
IPC分类号： G11C11/34
CPC分类号： G11C8/08 , G11C8/14
摘要： A word line driving circuit has a main word driver for producing first and second main word driver output signals and a subsidiary word driver for driving a word line. The subsidiary word driver has a load transistor supplied with the first main word driver output signal and a driver transistor supplied with the second word driver output signal. The subsidiary word driver has a state putting circuit for putting the word line into one of a high level, a low level, and a high impedance state.
摘要翻译：字线驱动电路具有用于产生第一和第二主字驱动器输出信号的主字驱动器和用于驱动字线的辅助字驱动器。辅助字驱动器具有提供有第一主字驱动器输出信号的负载晶体管和提供有第二字驱动器输出信号的驱动晶体管。辅助字驱动器具有用于将字线置于高电平，低电平和高阻抗状态之一的状态放置电路。

7. 发明授权

US6144613A Synchronous semiconductor memory 有权
标题翻译：同步半导体存储器
公开(公告)号：US6144613A
公开(公告)日：2000-11-07
申请号：US329716
申请日：1999-06-10
申请人： Yasushi Matsubara
发明人： Yasushi Matsubara
IPC分类号： G11C11/413 , G11C7/10 , G11C7/22 , G11C11/401 , G11C11/407 , G11C11/41 , G11C8/00
CPC分类号： G11C7/1072 , G11C7/22
摘要： According to one embodiment (100), a synchronous semiconductor memory may include a first initial circuit (102), second initial circuit (104) and third initial circuit (106). The first initial circuit (102) can receive an external clock signal CLK and compare the external clock signal CLK to a reference voltage VREF. The comparison result can be amplified and output as a signal .phi.1. The second initial circuit (104) can receive a clock control signal CKE and compare the clock control signal CKE to a reference voltage VREF. The comparison result can be amplified and output as a signal .phi.2. The third initial circuit (106) can receive the external clock signal CLK, and is activated by a control signal .phi.7 that can correspond to the clock enable signal CKE. The third initial circuit (106) can compare the external clock signal CLK to a reference voltage VREF, and amplify and output the comparison result .phi.8. The embodiment (100) can further include a first control circuit (108) that can receive the .phi.1 signal and generate a period signal .phi.3 having a constant pulse width that varies in synchronism with the external clock signal CLK. In addition, the first control circuit (108) can receive the .phi.8 signal and generate an internal clock signal .phi.5.
摘要翻译：根据一个实施例（100），同步半导体存储器可以包括第一初始电路（102），第二初始电路（104）和第三初始电路（106）。第一初始电路（102）可以接收外部时钟信号CLK并将外部时钟信号CLK与参考电压VREF进行比较。比较结果可以被放大并作为信号phi1输出。第二初始电路（104）可以接收时钟控制信号CKE并将时钟控制信号CKE与参考电压VREF进行比较。比较结果可以被放大并作为信号phi2输出。第三初始电路（106）可以接收外部时钟信号CLK，并由可对应于时钟使能信号CKE的控制信号phi7激活。第三初始电路（106）可以将外部时钟信号CLK与参考电压VREF进行比较，并且放大并输出比较结果phi 8.实施例（100）还可以包括可以接收phi的第一控制电路（108） 1信号，并产生具有与外部时钟信号CLK同步变化的恒定脉冲宽度的周期信号phi 3。此外，第一控制电路（108）可以接收phi 8信号并产生内部时钟信号phi 5。

8. 发明授权

US5764585A Semiconductor memory device having main word lines and sub word lines 失效
标题翻译：具有主字线和子字线的半导体存储器件
公开(公告)号：US5764585A
公开(公告)日：1998-06-09
申请号：US660281
申请日：1996-06-07
申请人： Yasushi Matsubara
发明人： Yasushi Matsubara
IPC分类号： G11C11/407 , G11C8/14 , G11C11/401 , G11C11/408 , G11C11/41 , H01L21/8242 , H01L27/108 , G11C8/00
CPC分类号： G11C8/14 , G11C11/408
摘要： In a DRAM device including a plurality of main row decoders and a plurality of sub row decoders, each of the main row decoders is connected to only one main word line. Each of the sub row decoders is connected to one main word line and a plurality of sub word lines. One or more of the sub word lines are activated in accordance with the activated main word line and the sub row decoders.
摘要翻译：在包括多个主行解码器和多个子行解码器的DRAM装置中，每个主行解码器仅连接一个主字线。每个子行解码器连接到一个主字线和多个子字线。一个或多个子字线根据激活的主字线和子行解码器被激活。

9. 发明授权

US5479044A Semiconductor circuit device capable of reducing influence of a parasitic capacitor 失效
标题翻译：能够减小寄生电容器的影响的半导体电路装置
公开(公告)号：US5479044A
公开(公告)日：1995-12-26
申请号：US263737
申请日：1994-06-22
申请人： Tetsuya Narahara , Yasushi Matsubara
发明人： Tetsuya Narahara , Yasushi Matsubara
IPC分类号： H01L23/64 , H01L27/06 , H01L27/07 , H03F3/45 , H01L27/02
CPC分类号： H01L27/0727 , H01L23/642 , H01L23/647 , H01L27/0688 , H03F3/45479 , H01L2924/0002
摘要： A semiconductor circuit device includes a differential amplifier circuit having a first parasitic capacitor formed between the semiconductor substrate and a first resistor and a second parasitic capacitor formed between the semiconductor substrate and a second resistor. Each of the first and the second resistors is implemented by a wiring pattern over the substrate so that the first and the second parasitic capacitors are equivalent to each other.
摘要翻译：半导体电路器件包括差分放大器电路，其具有形成在半导体衬底和第一电阻器之间的第一寄生电容器和形成在半导体衬底和第二电阻器之间的第二寄生电容器。第一和第二电阻器中的每一个由衬底上的布线图案实现，使得第一和第二寄生电容器彼此相同。

10. 发明授权

US10739985B2 Computer-readable storage medium having stored thereon display control program, display control system, display control apparatus, and display control method 有权
公开(公告)号：US10739985B2
公开(公告)日：2020-08-11
申请号：US12984944
申请日：2011-01-05
申请人： Yasushi Matsubara
发明人： Yasushi Matsubara
IPC分类号： G06F3/0488 , G06F3/0485 , A63F13/53
摘要： First, a plurality of selection objects having at least one part thereof displayed on a display area of a display device are moved relative to the display area, based on an output signal outputted from an input device. Then, when an end-located selection object among the moved plurality of selection objects reaches a predetermined position of the display area, an object that is different from the plurality of selection objects is displayed on the display area. The object moves relative to the display area based on an output signal outputted from the input device.

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