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    • 6. 发明授权
    • NAND nonvolatile semiconductor memory device and method of manufacturing NAND nonvolatile semiconductor memory device
    • NAND非易失性半导体存储器件和制造NAND非易失性半导体存储器件的方法
    • US07626235B2
    • 2009-12-01
    • US11812830
    • 2007-06-22
    • Hideyuki Kinoshita
    • Hideyuki Kinoshita
    • H01L29/76H01L29/94
    • H01L27/115H01L27/11521H01L27/11524
    • A NAND nonvolatile semiconductor memory device that has a memory cell array region and a selection gate region, has a semiconductor layer; a gate insulating film disposed on said semiconductor layer; a plurality of first electrode layers selectively disposed on said gate insulating film; a first device isolation insulating film formed in said memory cell array region and extends from between said adjacent first electrode layers into said semiconductor layer for device isolation; a second device isolation insulating film formed in said selection gate region and extends from between said adjacent first electrode layers into said semiconductor layer for device isolation; an interpoly insulating film formed at least on the top of said first electrode layers and said first device isolation insulating film in said memory cell array region; a second electrode layer disposed on said interpoly insulating film; and a third electrode layer disposed on said second electrode layer, said second device isolation insulating film and the first electrode layers in said selection gate region, wherein the height of the top surface of said second device isolation insulating film is greater than the height of the top surface of said first device isolation insulating film.
    • 具有存储单元阵列区域和选择栅极区域的NAND非易失性半导体存储器件具有半导体层; 设置在所述半导体层上的栅极绝缘膜; 选择性地设置在所述栅极绝缘膜上的多个第一电极层; 形成在所述存储单元阵列区域中并从所述相邻第一电极层之间延伸到所述半导体层中以进行器件隔离的第一器件隔离绝缘膜; 形成在所述选择栅极区中并从所述相邻的第一电极层之间延伸到所述半导体层中以用于器件隔离的第二器件隔离绝缘膜; 至少形成在所述存储单元阵列区域中的所述第一电极层和所述第一器件隔离绝缘膜的顶部上的多晶绝缘膜; 设置在所述多晶绝缘膜上的第二电极层; 以及设置在所述第二电极层上的第三电极层,所述第二器件隔离绝缘膜和所述选择栅极区中的第一电极层,其中所述第二器件隔离绝缘膜的顶表面的高度大于 所述第一器件隔离绝缘膜的顶表面。
    • 7. 发明申请
    • MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
    • 半导体器件和半导体器件的制造方法
    • US20080020530A1
    • 2008-01-24
    • US11829759
    • 2007-07-27
    • Hideyuki Kinoshita
    • Hideyuki Kinoshita
    • H01L21/336
    • H01L27/115H01L27/11521H01L27/11524
    • A manufacturing method of a semiconductor device disclosed herein, comprises: forming a first member to be patterned on a semiconductor substrate; forming a second member to be patterned on the first member; forming a third member to be patterned on the second member; patterning the third member to form a first line pattern and a first connecting portion in the third member, the first line pattern having a plurality of parallel linear patterns and the first connecting portion connecting the linear patterns on at least one end side of the linear patterns of the first line pattern; etching the second member with the third member as a mask to form a second line pattern and a second connecting portion in the second member, the second line pattern being the same pattern as the first line pattern and the second connecting portion being the same pattern as the first connecting portion; removing the second connecting portion of the second member; and etching the first member with the second member as a mask.
    • 本文公开的半导体器件的制造方法包括:在半导体衬底上形成待图案化的第一构件; 在第一构件上形成待图案化的第二构件; 在所述第二构件上形成要被图案化的第三构件; 图案化第三构件以在第三构件中形成第一线图案和第一连接部分,第一线图案具有多个平行线形图案,并且第一连接部分在线形图案的至少一端侧连接线图案 的第一行模式; 用第三构件作为掩模蚀刻第二构件以在第二构件中形成第二线图案和第二连接部分,第二线图案与第一线图案相同,图案与第二连接部分相同, 第一连接部分; 移除所述第二构件的所述第二连接部分; 并用第二部件作为掩模蚀刻第一部件。
    • 8. 发明申请
    • Method of manufacturing semiconductor device
    • 制造半导体器件的方法
    • US20070003881A1
    • 2007-01-04
    • US11453087
    • 2006-06-15
    • Eiji ItoHideyuki KinoshitaTetsuya KamigakiKoji Hashimoto
    • Eiji ItoHideyuki KinoshitaTetsuya KamigakiKoji Hashimoto
    • G03F7/26
    • G03F7/0035H01L2924/0002H01L2924/00
    • A method of manufacturing a semiconductor device includes forming a plurality of dummy line patterns arranged at a first pitch on an underlying region, forming first mask patterns having predetermined mask portions formed on long sides of the dummy line patterns, each of the first mask patterns having a closed-loop shape and surrounding each of the dummy line patterns, removing the dummy line patterns, forming a second mask pattern having a first pattern portion which covers end portions of the first mask patterns and inter-end portions each located between adjacent ones of the end portions, etching the underlying region using the first mask patterns and the second mask pattern as a mask to form trenches each located between adjacent ones of the predetermined mask portions, and filling the trenches with a predetermined material.
    • 一种制造半导体器件的方法包括在下面的区域上形成以第一间距布置的多个虚拟线图案,形成具有形成在虚拟线图案的长边上的预定掩模部分的第一掩模图案,每个第一掩模图案具有 闭环形状并且围绕每个虚拟线图案,去除虚拟线图案,形成具有第一图案部分的第二掩模图案,该第一图案部分覆盖第一掩模图案的端部和位于相邻的第一掩模图案的端部之间的端部部分 端部,使用第一掩模图案和第二掩模图案作为掩模蚀刻下面的区域,以形成各自位于相邻的预定掩模部分之间的沟槽,并且用预定的材料填充沟槽。
    • 9. 发明授权
    • Heat-sensitive stencil sheet
    • 热敏蜡纸
    • US06811866B1
    • 2004-11-02
    • US09395805
    • 1999-09-14
    • Hideyuki KinoshitaHiroshi Watanabe
    • Hideyuki KinoshitaHiroshi Watanabe
    • B32B900
    • B41N1/24Y10S428/913Y10T428/249987Y10T428/31
    • A heat-sensitive stencil sheet is provided, which is inhibited from jamming at the time of carrying or creasing at the time of winding around a drum, and thus excellent in carrying property and winding property. This heat-sensitive stencil sheet comprises a laminate of a thermoplastic resin film and a porous substrate mainly composed of synthetic fibers, and satisfies 0.150≦T−H wherein T denotes an arithmetic average value (g·cm/cm) of absolute values of KES bending torque in lengthwise direction of the stencil sheet at curvatures of +2.3 and −2.3 cm−1, H denotes a bending hysteresis (g·cm/cm), and T−H denotes a residual torque (g·cm/cm).
    • 提供了一种热敏蜡纸,其在绕着卷筒时被携带或压痕时被阻止,从而具有优异的承载性能和卷绕性能。 这种热敏蜡纸包括热塑性树脂膜和主要由合成纤维构成的多孔基材的层压体,并且满足0.150≤TTH,其中T表示KES弯曲绝对值的算术平均值(g.cm / cm) 曲线片长度方向的扭矩为+2.3和-2.3cm -1,H表示弯曲滞后(g.cm / cm),TH表示残余扭矩(g.cm / cm)。
    • 10. 发明授权
    • Semiconductor device having floating gate and method of producing the same
    • 具有浮动栅极的半导体器件及其制造方法
    • US06768161B2
    • 2004-07-27
    • US10157986
    • 2002-05-31
    • Hideyuki Kinoshita
    • Hideyuki Kinoshita
    • H01L29780
    • H01L27/11521H01L27/115
    • A semiconductor memory device, having at least one floating gate, includes a semiconductor substrate; at least one device-isolation region buried in the semiconductor substrate, having a top surface protruding from a top surface of the semiconductor substrate, the top surface of the device isolation region having a concave section that has a depression thereon; at least one gate-insulating film formed on the semiconductor substrate; a first gate formed on the gate-insulating film, the device-isolation region and the depression; a gate-to-gate insulating film formed on the first gate and in the concave section and the depression of the device-isolation region; and a second gate formed on the gate-to-gate insulation film, the depression being filled with the second gate.
    • 具有至少一个浮动栅极的半导体存储器件包括半导体衬底; 至少一个器件隔离区域,埋置在半导体衬底中,具有从半导体衬底的顶表面突出的顶表面,器件隔离区的顶表面具有凹陷部分; 形成在所述半导体基板上的至少一个栅极绝缘膜; 栅极绝缘膜上形成的第一栅极,器件隔离区域和凹陷部; 形成在所述第一栅极和所述凹部以及所述器件隔离区域的凹部中的栅极至栅极绝缘膜; 以及形成在所述栅极至栅极绝缘膜上的第二栅极,所述凹陷填充有所述第二栅极。