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1. 发明授权

US06703957B2 Digital-to-analog converter 失效
标题翻译：数模转换器
公开(公告)号：US06703957B2
公开(公告)日：2004-03-09
申请号：US10143878
申请日：2002-05-14
申请人： Yasuo Morimoto , Toshio Kumamoto , Takashi Okuda , Takahiro Miki
发明人： Yasuo Morimoto , Toshio Kumamoto , Takashi Okuda , Takahiro Miki
IPC分类号： H03M166
CPC分类号： H03M1/0614 , H03K5/01 , H03K5/133 , H03M1/822 , H03M3/372 , H03M3/506
摘要： When forming PDM pulses by a D/A converter in accordance with digital signals, the D/A converter causes at least one of the rising stage and the falling stage of each of the PDM pulses to change stepwise. In addition, when forming PWM pulses by another D/A converter, the D/A converter causes at least one of the rising stage and the falling stage of each of the PWM pulses to change stepwise.
摘要翻译：当通过D / A转换器根据数字信号形成PDM脉冲时，D / A转换器使得每个PDM脉冲的上升沿和下降沿中的至少一个逐步改变。此外，当由另一个D / A转换器形成PWM脉冲时，D / A转换器使每个PWM脉冲的上升沿和下降沿中的至少一个逐步改变。

2. 发明授权

US08237282B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08237282B2
公开(公告)日：2012-08-07
申请号：US13030861
申请日：2011-02-18
申请人： Takashi Okuda , Yasuo Morimoto , Yuko Maruyama , Toshio Kumamoto
发明人： Takashi Okuda , Yasuo Morimoto , Yuko Maruyama , Toshio Kumamoto
IPC分类号： H01L23/522
CPC分类号： H01L23/5223 , H01L23/5225 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.
摘要翻译：半导体器件包括：包括主表面的半导体衬底; 多个第一互连形成在形成在主表面上并沿预定方向延伸的电容形成区域中; 多个第二互连，每个相邻于位于电容形成区域的边缘处的第一互连，沿预定方向延伸并具有固定电位; 以及绝缘层，形成在主表面上，并且填充在每个第一互连之间以及第一互连和第二互连之间相邻。第一互连和第二互连在平行于主表面的平面中以基本相等的间隔定位，并且被定位成在基本上垂直于预定方向的方向上对齐。

3. 发明申请

US20090250788A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090250788A1
公开(公告)日：2009-10-08
申请号：US12485528
申请日：2009-06-16
申请人： Takashi OKUDA , Yasuo Morimoto , Yuko Maruyama , Toshio Kumamoto
发明人： Takashi OKUDA , Yasuo Morimoto , Yuko Maruyama , Toshio Kumamoto
IPC分类号： H01L29/00
CPC分类号： H01L23/5223 , H01L23/5225 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction, a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.
摘要翻译：半导体器件包括：包括主表面的半导体衬底; 形成在主表面上并沿预定方向延伸的电容形成区域中的多个第一互连，多个第二互连，每个第二互连相邻于位于电容形成区域边缘的第一互连件，沿预定方向延伸; 并具有固定的潜力; 以及绝缘层，形成在主表面上，并且填充在每个第一互连之间以及第一互连和第二互连之间相邻。第一互连和第二互连在平行于主表面的平面中以基本相等的间隔定位，并且被定位成在基本上垂直于预定方向的方向上对齐。

4. 发明授权

US07446390B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07446390B2
公开(公告)日：2008-11-04
申请号：US11845348
申请日：2007-08-27
申请人： Takashi Okuda , Yasuo Morimoto , Yuko Maruyama , Toshio Kumamoto
发明人： Takashi Okuda , Yasuo Morimoto , Yuko Maruyama , Toshio Kumamoto
IPC分类号： H01L29/00
CPC分类号： H01L23/5223 , H01L23/5225 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.
摘要翻译：半导体器件包括：包括主表面的半导体衬底; 多个第一互连形成在形成在主表面上并沿预定方向延伸的电容形成区域中; 多个第二互连，每个相邻于位于电容形成区域的边缘处的第一互连，沿预定方向延伸并具有固定电位; 以及绝缘层，形成在主表面上，并且填充在每个第一互连之间以及第一互连和第二互连之间相邻。第一互连和第二互连在平行于主表面的平面中以基本相等的间隔定位，并且被定位成在基本上垂直于预定方向的方向上对齐。

5. 发明申请

US20080001255A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20080001255A1
公开(公告)日：2008-01-03
申请号：US11845348
申请日：2007-08-27
申请人： Takashi OKUDA , Yasuo Morimoto , Yuko Maruyama , Toshio Kumamoto
发明人： Takashi OKUDA , Yasuo Morimoto , Yuko Maruyama , Toshio Kumamoto
IPC分类号： H01L29/00
CPC分类号： H01L23/5223 , H01L23/5225 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.
摘要翻译：半导体器件包括：包括主表面的半导体衬底; 多个第一互连形成在形成在主表面上并沿预定方向延伸的电容形成区域中; 多个第二互连，每个相邻于位于电容形成区域的边缘处的第一互连，沿预定方向延伸并具有固定电位; 以及绝缘层，形成在主表面上，并且填充在每个第一互连之间以及第一互连和第二互连之间相邻。第一互连和第二互连在平行于主表面的平面中以基本相等的间隔定位，并且被定位成在基本上垂直于预定方向的方向上对齐。

6. 发明授权

US06573588B1 Capacitance element 失效
标题翻译：电容元件
公开(公告)号：US06573588B1
公开(公告)日：2003-06-03
申请号：US10278943
申请日：2002-10-24
申请人： Toshio Kumamoto , Takashi Okuda , Yasuo Morimoto
发明人： Toshio Kumamoto , Takashi Okuda , Yasuo Morimoto
IPC分类号： H01L2900
CPC分类号： H01L29/92 , H01L29/94
摘要： A P well region formed on a buried N well region and a n+ active region that are connected each other through a lead wire, serve as one terminal T1, and a gate electrode and a buried N well region that are connected each other through a leading N well region and a lead wire, serve as the other terminal T2. Thereby, the voltage dependence of capacitance C1 formed between the gate electrode and the n+ active region is canceled out with the voltage dependence of capacitance C2 formed between the P well region and the buried N well region.
摘要翻译： AP阱区域形成在通过引线彼此连接的掩埋N阱区域和n +有源区域上，用作一个端子T1，以及通过前导N相互连接的栅电极和掩埋N阱区域井区和导线，作为另一个终端T2。由此，在P阱区域和掩埋N阱区域之间形成的电容C2的电压依赖性抵消在栅电极和n +有源区域之间形成的电容C1的电压依赖性。

7. 发明授权

US07276776B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07276776B2
公开(公告)日：2007-10-02
申请号：US11013514
申请日：2004-12-17
申请人： Takashi Okuda , Yasuo Morimoto , Yuko Maruyama , Toshio Kumamoto
发明人： Takashi Okuda , Yasuo Morimoto , Yuko Maruyama , Toshio Kumamoto
IPC分类号： H01L29/00
CPC分类号： H01L23/5223 , H01L23/5225 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.
摘要翻译：半导体器件包括：包括主表面的半导体衬底; 多个第一互连形成在形成在主表面上并沿预定方向延伸的电容形成区域中; 多个第二互连，每个相邻于位于电容形成区域的边缘处的第一互连，沿预定方向延伸并具有固定电位; 以及绝缘层，形成在主表面上，并且填充在每个第一互连之间以及第一互连和第二互连之间相邻。第一互连和第二互连在平行于主表面的平面中以基本相等的间隔定位，并且被定位成在基本上垂直于预定方向的方向上对准。

8. 发明申请

US20050145987A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20050145987A1
公开(公告)日：2005-07-07
申请号：US11013514
申请日：2004-12-17
申请人： Takashi Okuda , Yasuo Morimoto , Yuko Maruyama , Toshio Kumamoto
发明人： Takashi Okuda , Yasuo Morimoto , Yuko Maruyama , Toshio Kumamoto
IPC分类号： H01L21/3205 , H01L21/768 , H01L21/822 , H01L23/52 , H01L23/522 , H01L27/04 , H01L29/76
CPC分类号： H01L23/5223 , H01L23/5225 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.
摘要翻译：半导体器件包括：包括主表面的半导体衬底; 多个第一互连形成在形成在主表面上并沿预定方向延伸的电容形成区域中; 多个第二互连，每个相邻于位于电容形成区域的边缘处的第一互连，沿预定方向延伸并具有固定电位; 以及绝缘层，形成在主表面上，并且填充在每个第一互连之间以及第一互连和第二互连之间相邻。第一互连和第二互连在平行于主表面的平面中以基本相等的间隔定位，并且被定位成在基本上垂直于预定方向的方向上对齐。

9. 发明授权

US06734814B2 Modulator 有权
标题翻译：调制器
公开(公告)号：US06734814B2
公开(公告)日：2004-05-11
申请号：US10167460
申请日：2002-06-14
申请人： Takashi Okuda , Toshio Kumamoto , Yasuo Morimoto
发明人： Takashi Okuda , Toshio Kumamoto , Yasuo Morimoto
IPC分类号： H03M300
CPC分类号： H03M7/3006 , H03M3/368 , H03M3/418 , H03M3/43 , H03M3/45 , H03M3/452 , H03M7/3022 , H03M7/3028 , H03M7/3033 , H03M7/3037
摘要： In a modulator, an attenuator attenuates an input signal, a delay element gives a delay of 1 sample period to the attenuated signal, an adder subtracts a quantized signal that has been fed back with a delay of 1 sample period, from the delayed signal, two or more integrators integrate a result of the subtraction, an adder which adds outputs of the respective integrators and the attenuated signal, and a quantizer quantizes a result of the addition, outputs a result of the quantization as an output signal and feeds back the output signal to the subtractor.
摘要翻译：在调制器中，衰减器衰减输入信号，延迟元件给衰减信号提供1个采样周期的延迟，加法器从延迟信号中减去已经以1个采样周期的延迟反馈的量化信号，两个或更多个积分器集成减法的结果，加上各积分器的输出的加法器和衰减的信号，量化器对加法的结果进行量化，输出量化的结果作为输出信号，反馈输出发信号给减法器。

10. 发明授权

US06323794B1 &Dgr;&Sgr; modulator, DA converter and AD converter 有权
标题翻译： DELTASIGMA调制器，DA转换器和AD转换器
公开(公告)号：US06323794B1
公开(公告)日：2001-11-27
申请号：US09437405
申请日：1999-11-10
申请人： Takashi Okuda , Toshio Kumamoto , Yasuo Morimoto
发明人： Takashi Okuda , Toshio Kumamoto , Yasuo Morimoto
IPC分类号： H03M300
CPC分类号： H03M7/3022 , H03M3/414 , H03M3/458 , H03M3/50
摘要： Modulators (M1 to Mk (k≧2)) are connected in a multi-stage such that each of quantization errors (e1, e2, . . . ) of the modulators (M1 to Mk−1) is fed to the input of the next stage modulator. Each output signal of the modulators (M2 to Mk) is fed back to the input of the immediately preceding modulator. The modulators (M1 to Mk) are all first-order modulators. Only the final stage modulator (Mk) has a multi-bit quantizer (6), and all the preceding modulators (M1 to Mk−1) have an 1-bit quantizer (3). Accordingly, a noise-shaping equal to that of a multi-bit higher-order modulator is realized on a small-scale circuit while retaining stability.
摘要翻译：调制器（M1至Mk（k> = 2））以多级连接，使得调制器（M1至Mk-1）的每个量化误差（e1，e2，...）被馈送到下一级调制器。调制器（M2至Mk）的每个输出信号被反馈到紧接在前的调制器的输入端。调制器（M1至Mk）都是一阶调制器。只有最后级调制器（Mk）具有多位量化器（6），并且所有先前的调制器（M1至Mk-1）都具有1位量化器（3）。因此，在保持稳定性的同时，在小规模电路上实现等于多位高阶调制器的噪声整形。

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