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1. 发明授权

US5235313A Thin film resistor and wiring board using the same 失效
标题翻译：薄膜电阻和使用其的接线板
公开(公告)号：US5235313A
公开(公告)日：1993-08-10
申请号：US723608
申请日：1991-07-01
申请人： Yasunori Narizuka , Syoozi Ikeda , Akira Yabushita , Masakazu Ishino , Juichi Kishida
发明人： Yasunori Narizuka , Syoozi Ikeda , Akira Yabushita , Masakazu Ishino , Juichi Kishida
IPC分类号： B41J2/335 , H01C7/00 , H05B3/12 , H05B3/14
CPC分类号： B41J2/33515 , B41J2/3355 , B41J2/3356 , B41J2/33565 , B41J2/3357 , B41J2/3359 , H01C7/006
摘要： A thin film resistor having a characteristic that an increase phenomenon of a resistance controlled at a high temperature is generated. The resistor is obtained by controlling its composition and manufacturing method so as to suppress an increase in the resistance of a Cr-Si resistor thin film due to deposition of chromium silicide at a high temperature. A sputtering target, which is used as a raw material for forming the thin film, is made from chromium silicide and silicon so that some chromium silicide is already formed immediately after deposition, and chromium oxide and silicon oxide are contained in the thin film so as to suppress the speed whereat chromium and silicon, which do not form silicide, form silicide by heating after deposition and to allow the above silicide formation to advance slowly.
摘要翻译：具有产生在高温下控制的电阻增加现象的特性的薄膜电阻器。通过控制其组成和制造方法来获得电阻器，以便抑制由于在高温下沉积硅化铬导致的Cr-Si电阻器薄膜的电阻增加。用作形成薄膜的原料的溅射靶由硅化铬和硅制成，使得沉积后立即形成一些硅化铬，并且氧化铬和氧化硅被包含在薄膜中，以便抑制不形成硅化物的铬和硅在沉积后通过加热形成硅化物，并允许上述硅化物形成缓慢进行。

2. 发明授权

US5285016A Wiring board provided with a heat bypass layer 失效
标题翻译：接线板配有热旁路层
公开(公告)号：US5285016A
公开(公告)日：1994-02-08
申请号：US618407
申请日：1990-11-27
申请人： Yasunori Narizuka , Akihiro Kemmotsu , Masakazu Ishino , Eiji Matsuzaki
发明人： Yasunori Narizuka , Akihiro Kemmotsu , Masakazu Ishino , Eiji Matsuzaki
IPC分类号： H05K1/02 , H01L23/367 , H01L23/538 , H01L27/01 , H05K1/16 , H05K3/38 , H05K3/46 , H05K1/00
CPC分类号： H05K1/0203 , H01L23/3677 , H01L23/538 , H05K3/388 , H01L2924/0002 , H05K2201/0195 , H05K3/4644
摘要： Disclosed herein are high density wiring boards useful in computers, communication equipment and the like. They include a layer for bypassing heat to be generated. Heat generated at a conductor and/or a resistor in each wiring board is allowed to spread out evenly via the heat bypass layer.
摘要翻译：这里公开了可用于计算机，通信设备等的高密度线路板。它们包括用于绕过要产生的热量的层。在每个接线板中的导体和/或电阻器处产生的热量允许通过热旁路层均匀地分布。

3. 发明授权

US5320729A Sputtering target 失效
标题翻译：溅射目标
公开(公告)号：US5320729A
公开(公告)日：1994-06-14
申请号：US914469
申请日：1992-07-17
申请人： Yasunori Narizuka , Masakazu Ishino , Akihiro Kenmotsu , Yoshitaka Chiba , Akitoshi Hiraki
发明人： Yasunori Narizuka , Masakazu Ishino , Akihiro Kenmotsu , Yoshitaka Chiba , Akitoshi Hiraki
IPC分类号： C23C14/34
CPC分类号： H01J37/3426 , H01J37/3491
摘要： Disclosed herein is a sputtering target with which a high resistivity thin film consisting of chromium, silicon and oxygen can be produced economically and stably for a long time. Also disclosed is a process for producing the sputtering target by selecting the grain size of a chromium (Cr) powder and a silicon dioxide (SiO.sub.2) powder, drying the powders sufficiently by heating, then mixing the dried powders to obtain a mixed powder containing generally from 20 to 80% by weight of chromium, most preferably from 50 to 80% by weight of chromium, the remainder being silicon dioxide, packing the mixed powder in a die, and sintering the packed powder by hot pressing or the like, to produce a desired sputtering target which has a two phase mixed structure. The sputtering target can be used for manufacture of thin film resistors and electric circuits.
摘要翻译：本文公开了一种溅射靶，其可以经济地且稳定地长时间生产由铬，硅和氧组成的高电阻率薄膜。还公开了通过选择铬（Cr）粉末和二氧化硅（SiO 2）粉末的晶粒尺寸来制造溅射靶的方法，通过加热将粉末充分干燥，然后混合干燥粉末，得到通常含有的混合粉末 20至80重量％的铬，最优选为50至80重量％的铬，其余为二氧化硅，将混合粉末包装在模具中，并通过热压等烧结填充的粉末，以产生具有两相混合结构的期望的溅射靶。溅射靶可用于薄膜电阻和电路的制造。

4. 发明授权

US08513121B2 Semiconductor memory device and manufacturing method thereof 失效
公开(公告)号：US08513121B2
公开(公告)日：2013-08-20
申请号：US13621134
申请日：2012-09-15
申请人： Masakazu Ishino , Hiroaki Ikeda , Kayoko Shibata
发明人： Masakazu Ishino , Hiroaki Ikeda , Kayoko Shibata
IPC分类号： H01L21/44 , H01L21/48
CPC分类号： H01L21/6835 , G11C5/02 , G11C5/025 , H01L23/481 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2224/05573 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2224/81005 , H01L2224/94 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2225/06555 , H01L2225/06572 , H01L2225/06586 , H01L2225/06596 , H01L2924/00014 , H01L2924/15311 , H01L2924/1532 , H01L2924/15787 , H01L2924/181 , H01L2924/30105 , H01L2224/81 , H01L2924/00 , H01L2224/05599 , H01L2924/00012
摘要： A semiconductor memory device has a plurality of core chips and an interface chip, whose specification can be easily changed, while suppressing the degradation of its reliability. The device has an interposer chip. First internal electrodes connected to core chips are formed on the first surface of the interposer chip. Second internal electrodes connected to an interface chip and third internal electrodes connected to external electrodes are formed on the second surface of the interposer chip. The interface chip can be mounted on the second surface of the interposer chip whenever desired. Therefore, the memory device can have any specification desirable to a customer, only if an appropriate interface chip is mounted on the interposer chip, as is demanded by the customer. Thus, the core chips do not need to be stocked in great quantities in the form of bare chips.

5. 发明授权

US08334465B2 Wafer of circuit board and joining structure of wafer or circuit board 有权
标题翻译：电路板晶圆和晶圆或电路板的接合结构
公开(公告)号：US08334465B2
公开(公告)日：2012-12-18
申请号：US12285222
申请日：2008-09-30
申请人： Masakazu Ishino , Hiroaki Ikeda , Hideharu Miyake , Shiro Uchiyama , Hiroyuki Tenmei , Kunihiko Nishi , Yasuhiro Naka , Nae Hisano
发明人： Masakazu Ishino , Hiroaki Ikeda , Hideharu Miyake , Shiro Uchiyama , Hiroyuki Tenmei , Kunihiko Nishi , Yasuhiro Naka , Nae Hisano
IPC分类号： H05K1/16 , H05K1/00 , H05K1/03 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H05K1/0296 , H01L23/481 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/12 , H01L24/16 , H01L24/81 , H01L24/90 , H01L25/0657 , H01L2224/03912 , H01L2224/0401 , H01L2224/05599 , H01L2224/1147 , H01L2224/11901 , H01L2224/11902 , H01L2224/13099 , H01L2224/13111 , H01L2224/2518 , H01L2224/81193 , H01L2224/81801 , H01L2224/90 , H01L2225/06513 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H05K1/09 , H05K3/3436 , H05K2201/0367 , H05K2201/10674 , Y02P70/613
摘要： A wafer (or a circuit board), which is used to perform three-dimensional mounting, has protrusion 20 which is provided in low melting point metal 15 for electrically connecting mutually joined wafers 61 and 62, and which defines an interval between mutually joined wafers 61 and 62 without being deformed at the time when low melting point metal 15 is melted. A joining structure of wafers 61 and 62 is manufactured by using wafers 61 and 62, at least one of which has protrusion 20. In the manufactured joining structure of wafers 61 and 62, wafers 61 and 62 are electrically connected to each other by low melting point metal 15, and protrusion 20, which defines the interval between wafers 61 and 62 without being deformed at the time when low melting point metal 15 is melted, is provided in low melting point metal 15.
摘要翻译：用于进行三维安装的晶片（或电路板）具有突起20，该突起20设置在用于电连接相互接合的晶片61和62的低熔点金属15中，并且限定相互连接的晶片之间的间隔 61和62，在低熔点金属15熔化时不变形。通过使用晶片61和62中的至少一个具有突起20来制造晶片61和62的接合结构。在制造的晶片61和62的接合结构中，晶片61和62通过低熔点彼此电连接点金属15和在低熔点金属15熔化时不会变形的晶片61和62之间的间隔的突起20设置在低熔点金属15中。

6. 发明授权

US07893540B2 Semiconductor memory device and manufacturing method thereof 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US07893540B2
公开(公告)日：2011-02-22
申请号：US12537723
申请日：2009-08-07
申请人： Masakazu Ishino , Hiroaki Ikeda , Kayoko Shibata
发明人： Masakazu Ishino , Hiroaki Ikeda , Kayoko Shibata
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L21/6835 , G11C5/02 , G11C5/025 , H01L23/481 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2224/05573 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2224/81005 , H01L2224/94 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2225/06555 , H01L2225/06572 , H01L2225/06586 , H01L2225/06596 , H01L2924/00014 , H01L2924/15311 , H01L2924/1532 , H01L2924/15787 , H01L2924/181 , H01L2924/30105 , H01L2224/81 , H01L2924/00 , H01L2224/05599 , H01L2924/00012
摘要： A semiconductor memory device has a plurality of core chips and an interface chip, whose specification can be easily changed, while suppressing the degradation of its reliability. The device has an interposer chip. First internal electrodes connected to core chips are formed on the first surface of the interposer chip. Second internal electrodes connected to an interface chip and third internal electrodes connected to external electrodes are formed on the second surface of the interposer chip. The interface chip can be mounted on the second surface of the interposer chip whenever desired. Therefore, the memory device can have any specification desirable to a customer, only if an appropriate interface chip is mounted on the interposer chip, as is demanded by the customer. Thus, the core chips do not need to be stocked in great quantities in the form of bare chips.
摘要翻译：半导体存储器件具有多个芯片和接口芯片，其规格可以容易地改变，同时抑制其可靠性的劣化。该器件具有插入器芯片。连接到芯片的第一内部电极形成在插入器芯片的第一表面上。连接到接口芯片的第二内部电极和连接到外部电极的第三内部电极形成在插入器芯片的第二表面上。只要需要，接口芯片可以安装在插入器芯片的第二表面上。因此，只要客户要求的适当的接口芯片安装在插入器芯片上，存储器件就可以具有对客户所期望的任何规格。因此，核心芯片不需要以裸芯片的形式大量存放。

7. 发明申请

US20080009124A1 Method of forming a semiconductor device 审中-公开
标题翻译：形成半导体器件的方法
公开(公告)号：US20080009124A1
公开(公告)日：2008-01-10
申请号：US11824626
申请日：2007-07-02
申请人： Masakazu Ishino , Hiroaki Ikeda
发明人： Masakazu Ishino , Hiroaki Ikeda
IPC分类号： H01L21/00
CPC分类号： H01L23/3114 , H01L21/78 , H01L25/0652 , H01L25/50 , H01L2224/05001 , H01L2224/05009 , H01L2224/05147 , H01L2224/05568 , H01L2224/05655 , H01L2224/16 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/15311 , H01L2924/00014
摘要： A method of forming a semiconductor device includes the following processes. A semiconductor wafer including chips and through electrodes is diced into chip groups. The chip groups are stacked to form a module group.
摘要翻译：形成半导体器件的方法包括以下处理。将包括芯片和通孔的半导体晶片切成芯片组。堆叠芯片组以形成模块组。

8. 发明授权

US08704352B2 Semiconductor device having a liquid cooling module 有权
标题翻译：具有液体冷却模块的半导体装置
公开(公告)号：US08704352B2
公开(公告)日：2014-04-22
申请号：US12683085
申请日：2010-01-06
申请人： Nae Hisano , Shigeo Ohashi , Yasuo Osone , Yasuhiro Naka , Hiroyuki Tenmei , Kunihiko Nishi , Hiroaki Ikeda , Masakazu Ishino , Hideharu Miyake , Shiro Uchiyama
发明人： Nae Hisano , Shigeo Ohashi , Yasuo Osone , Yasuhiro Naka , Hiroyuki Tenmei , Kunihiko Nishi , Hiroaki Ikeda , Masakazu Ishino , Hideharu Miyake , Shiro Uchiyama
IPC分类号： H01L23/02 , H01L23/34
CPC分类号： H01L24/14 , H01L23/3128 , H01L23/34 , H01L23/473 , H01L2224/16145 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2225/06565 , H01L2924/1461 , H01L2924/15311 , H01L2924/15321 , H01L2924/181 , H01L2924/18161 , H01L2924/00
摘要： A semiconductor device comprises a mounting substrate, a semiconductor element provided above said mounting substrate, a package substrate provided above said mounting substrate with said semiconductor element therebetween and electrically connected to said semiconductor element via a primary connecting bump, a liquid cooling module cooling said semiconductor element by a liquid refrigerant, in which a heat receiving section of the liquid cooling module is disposed between said semiconductor element and said mounting substrate, and a plurality of secondary connecting bumps provided between said package substrate and said mounting substrate.
摘要翻译：半导体器件包括安装基板，设置在所述安装基板上方的半导体元件，设置在所述安装基板上方的封装基板，其间具有所述半导体元件，并通过主连接凸块与所述半导体元件电连接;冷却所述半导体液体制冷剂的热接收部分设置在所述半导体元件和所述安装基板之间，以及设置在所述封装基板和所述安装基板之间的多个次级连接凸块。

9. 发明授权

US07618847B2 Bonding method of semiconductor and laminated structure fabricated thereby 失效
标题翻译：由此制造的半导体和层压结构的接合方法
公开(公告)号：US07618847B2
公开(公告)日：2009-11-17
申请号：US12187622
申请日：2008-08-07
申请人： Hiroyuki Tenmei , Kunihiko Nishi , Yasuhiro Naka , Nae Hisano , Hiroaki Ikeda , Masakazu Ishino
发明人： Hiroyuki Tenmei , Kunihiko Nishi , Yasuhiro Naka , Nae Hisano , Hiroaki Ikeda , Masakazu Ishino
IPC分类号： H01L21/00
CPC分类号： H01L24/73 , H01L21/76898 , H01L23/544 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L24/83 , H01L24/92 , H01L24/94 , H01L25/50 , H01L2223/5442 , H01L2223/54426 , H01L2223/54453 , H01L2224/05001 , H01L2224/05023 , H01L2224/0508 , H01L2224/05147 , H01L2224/05166 , H01L2224/05169 , H01L2224/05171 , H01L2224/05184 , H01L2224/05568 , H01L2224/05655 , H01L2224/1146 , H01L2224/11462 , H01L2224/1147 , H01L2224/11849 , H01L2224/11912 , H01L2224/13083 , H01L2224/13084 , H01L2224/13111 , H01L2224/13147 , H01L2224/13155 , H01L2224/13166 , H01L2224/2919 , H01L2224/73104 , H01L2224/75753 , H01L2224/8113 , H01L2224/81191 , H01L2224/81192 , H01L2224/81203 , H01L2224/81205 , H01L2224/81815 , H01L2224/831 , H01L2224/83191 , H01L2224/83203 , H01L2224/83205 , H01L2224/83856 , H01L2224/83862 , H01L2224/83871 , H01L2224/83907 , H01L2224/9211 , H01L2224/94 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/00014 , H01L2224/11 , H01L2224/81 , H01L2224/27
摘要： A bonding method (three-dimensional mounting) of semiconductor substrates is provided to sequentially bond a principal surface of a silicon wafer on which coupling bumps are formed, and a principal surface of the other silicon wafer on which pads are formed, by an adhesive applied to at least one of the principal surfaces. However, there is a problem of poor electrical coupling due to displacement of the bumps and the pads when bonded together. The present invention solves such a problem by conducting temporary positioning of the silicon wafers, adjusting the positions of the coupling bumps and pads while confirming the positions by a method such as x-ray capable of passing through the silicon wafers, and bonding the bumps and the pads together while hardening an interlayer adhesive provided between the principal surfaces of the silicon wafers by thermocompression.
摘要翻译：提供半导体衬底的接合方法（三维安装），以通过施加的粘合剂顺序地接合形成有耦合凸块的硅晶片的主表面和形成有焊盘的另一个硅晶片的主表面到至少一个主表面。然而，由于当焊接在一起时由于凸起和焊盘的位移而存在差的电耦合的问题。本发明通过进行硅晶片的临时定位来解决这样的问题，通过诸如能够通过硅晶片的x射线的方法确认位置来确定位置，并且将凸块和一边通过热压而使设置在硅晶片的主表面之间的层间粘合剂硬化。

10. 发明授权

US07564127B2 Memory module that is capable of controlling input/output in accordance with type of memory chip 有权
标题翻译：能够根据存储器芯片的类型控制输入/输出的存储器模块
公开(公告)号：US07564127B2
公开(公告)日：2009-07-21
申请号：US11404785
申请日：2006-04-17
申请人： Hiroaki Ikeda , Masakazu Ishino
发明人： Hiroaki Ikeda , Masakazu Ishino
IPC分类号： H01L23/02 , H01L21/44
CPC分类号： G11C7/10 , G11C5/02 , G11C5/063 , H01L25/18 , H01L2224/0401 , H01L2224/0557 , H01L2224/13025 , H01L2224/16145 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2924/0002 , H01L2924/01055 , H01L2924/15192 , H01L2924/15311 , H01L2224/05552
摘要： A memory module of the present invention is provided with a memory core chip that is placed between an interface chip and an interposer chip and has a relay wire for electrically connecting these chips, an interposer chip that transmits type-information, that is information showing the type of the memory core chip, to the interface chip through the relay wire, and the interface chip that controls the memory core chip in accordance with the type-information received from the interposer chip.
摘要翻译：本发明的存储器模块设置有存储芯片芯片，其被置于接口芯片和插入器芯片之间，并且具有用于电连接这些芯片的中继线，传送类型信息的插入器芯片，即表示存储器核心芯片的类型，通过继电器线的接口芯片，以及根据从插入器芯片接收的类型信息来控制存储器核心芯片的接口芯片。

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