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1. 外观设计

USD289986S Four wheeled motorcycle 失效
公开(公告)号：USD289986S
公开(公告)日：1987-05-26
申请号：US604743
申请日：1984-04-27
申请人： Yasuhiro Ooba , Mitsuru Yamamoto , Shiro Miyamoto
设计人： Yasuhiro Ooba , Mitsuru Yamamoto , Shiro Miyamoto

2. 外观设计

USD286760S Four wheel vehicle 失效
公开(公告)号：USD286760S
公开(公告)日：1986-11-18
申请号：US613512
申请日：1984-05-23
申请人： Yasuhiro Ooba , Kazuhiko Saito , Mitsuru Yamamoto
设计人： Yasuhiro Ooba , Kazuhiko Saito , Mitsuru Yamamoto

3. 发明授权

US07035216B2 Congestion control unit 失效
标题翻译：拥塞控制单元
公开(公告)号：US07035216B2
公开(公告)日：2006-04-25
申请号：US09981095
申请日：2001-10-16
申请人： Yukihiro Kikuchi , Syuji Takada , Yasuhiro Ooba
发明人： Yukihiro Kikuchi , Syuji Takada , Yasuhiro Ooba
IPC分类号： H04L1/00
CPC分类号： H04L47/30 , H04L47/10 , H04L47/12 , H04L47/32 , H04L69/16 , H04L69/163
摘要： The present invention relates to a packet transfer communication device. More particularly, the present invention relates to a congestion control unit designed to handle communication at high speed by reducing a load of congestion processing conducted in a core router and an edge router. The congestion control unit includes a packet discarding judgment section that conducts congestion control by a packet discarding judgment based on a smooth queue length which is a quantity of accumulated data composed of a difference between a quantity of input data and a quantity of output data at each predetermined period in a smooth queue length calculating section.
摘要翻译：分组传送通信装置技术领域本发明涉及一种分组传送通信装置。更具体地，本发明涉及一种拥塞控制单元，其设计为通过减少在核心路由器和边缘路由器中进行的拥塞处理的负担来高速处理通信。拥塞控制单元包括：分组丢弃判断部，其基于平滑队列长度进行分组丢弃判断的拥塞控制，该平滑队列长度是由输入数据量和每个输出数据的数量之间的差构成的累积数据量平滑队列长度计算部分的预定时间段。

4. 发明授权

US06826673B2 Communications protocol processing by real time processor off-loading operations to queue for processing by non-real time processor 失效
标题翻译：通信协议处理通过实时处理器卸载操作进行队列处理，由非实时处理器
公开(公告)号：US06826673B2
公开(公告)日：2004-11-30
申请号：US09775160
申请日：2001-02-01
申请人： Takeshi Toyoyama , Masao Nakano , Yasuhiro Ooba
发明人： Takeshi Toyoyama , Masao Nakano , Yasuhiro Ooba
IPC分类号： G06F15167
CPC分类号： H04Q11/0478 , H04L2012/5651 , H04L2012/5671
摘要： A communication protocol processing unit by a multiprocessor is disclosed, and includes a first processor for performing a process demanding a real time property on a stream of communication data; and a second processor for performing a process not demanding the real time property, wherein the first processor transfers using parameters paired with the communication data to be processed to the second processor, and the second processor is structured so as to refer to the transferred communication data and parameters to process.
摘要翻译：公开了一种通过多处理器的通信协议处理单元，并且包括：第一处理器，用于执行要求通信数据流上的实时属性的处理; 以及用于执行不要求实时性的处理的第二处理器，其中所述第一处理器使用与要处理的所述通信数据配对的参数来传送到所述第二处理器，并且所述第二处理器被构造为参考所传送的通信数据和参数进行处理。

5. 发明授权

US07149184B2 Transmission rate monitoring apparatus and method 有权
标题翻译：传输速率监测装置及方法
公开(公告)号：US07149184B2
公开(公告)日：2006-12-12
申请号：US09858611
申请日：2001-05-16
申请人： Syuji Takada , Yasuhiro Ooba
发明人： Syuji Takada , Yasuhiro Ooba
IPC分类号： H04J1/16 , H04J3/14
CPC分类号： H04L47/36 , H04L25/0262 , H04L47/10 , H04L47/11 , H04L47/20 , H04L47/21 , H04L47/215 , H04L47/32
摘要： A transmission rate monitoring apparatus capable of promptly detecting the average transmission rate of data transmitted on a transmission channel. Data is received on the transmission channel, and a desired average transmission rate is set with respect to a predetermined time period. The amount of data received is measured and data is accepted or discarded in accordance with the data amount measured within the predetermined time period and the average transmission rate.
摘要翻译：一种能够及时检测在传输信道上发送的数据的平均传输速率的传输速率监视装置。在传输信道上接收数据，并且相对于预定时间段设置期望的平均传输速率。测量接收到的数据量，并根据在预定时间段内测量的数据量和平均传输速率接收或丢弃数据。

6. 发明授权

US07075938B1 Common buffer memory control apparatus 失效
标题翻译：公共缓冲存储器控制装置
公开(公告)号：US07075938B1
公开(公告)日：2006-07-11
申请号：US09258442
申请日：1999-02-26
申请人： Syuji Takada , Yasuhiro Ooba
发明人： Syuji Takada , Yasuhiro Ooba
IPC分类号： H04L12/28
CPC分类号： H04L49/901 , H04L49/103 , H04L49/108 , H04L49/90 , H04L49/9036
摘要： A common buffer memory control apparatus controls a common buffer memory which is used to store message data items each of which is divided into a plurality of cells based on an asynchronous transfer mode. The common buffer memory control apparatus includes a free block management table for managing whether each of blocks into which the common buffer memory divided is free or used, a block selecting unit for selecting a block of the common buffer memory which is free with reference to the free block management table, and a cell writing control unit for controlling a write operation for cells of a single message data item so that the respective cells of the single message data item are written in the block, selected by the block selecting means, of the common buffer memory.
摘要翻译：公共缓冲存储器控制装置控制公共缓冲存储器，其用于存储基于异步传输模式将消息数据项分为多个单元的消息数据项。公共缓冲存储器控制装置包括一个空闲块管理表，用于管理被分配的公共缓冲存储器中的每个块是空闲还是使用的块;块选择单元，用于选择公共缓冲存储器的块，空闲块管理表和单元写入控制单元，用于控制单个消息数据项的单元的写入操作，使得单个消息数据项的各个单元被写入由块选择装置选择的块中公共缓冲存储器。

7. 发明授权

US06895473B2 Data control device and an ATM control device 有权
标题翻译：数据控制装置和ATM控制装置
公开(公告)号：US06895473B2
公开(公告)日：2005-05-17
申请号：US10298973
申请日：2002-11-12
申请人： Masao Nakano , Takeshi Toyoyama , Yasuhiro Ooba
发明人： Masao Nakano , Takeshi Toyoyama , Yasuhiro Ooba
IPC分类号： G06F15/167 , G06F15/173 , H04L12/70 , H04L12/937 , H04Q11/04 , G06F12/00
CPC分类号： H04Q11/0478 , H04L2012/5625
摘要： A data control device capable of high-quality, high-efficiency control for speeding up data processing, thus permitting improvement of the throughput of a system. Attribute analyzing unit analyzes an attribute of data, and a main memory stores setting information of the data in a region corresponding to the attribute. A highway cache memory stores the data, and also receives and transmits the data on a highway. A processor performs an operation on the data in accordance with the setting information. A data cache memory is interposed between the processor and the main memory and stores the setting information.
摘要翻译：一种能够进行高质量，高效率控制的数据控制装置，用于加速数据处理，从而可以提高系统的吞吐量。属性分析单元分析数据的属性，并且主存储器将数据的设置信息存储在与属性相对应的区域中。公路缓存存储器存储数据，并且还在高速公路上接收和发送数据。处理器根据设置信息对数据进行操作。在处理器和主存储器之间插入数据高速缓冲存储器并存储设置信息。

8. 发明授权

US06633961B2 Buffer apparatus with data insertion control function, insertion data controlling method, and data insertion apparatus with data insertion control function 失效
标题翻译：具有数据插入控制功能的缓冲装置，插入数据控制方法以及具有数据插入控制功能的数据插入装置
公开(公告)号：US06633961B2
公开(公告)日：2003-10-14
申请号：US10067453
申请日：2002-02-05
申请人： Syuji Takada , Yasuhiro Ooba
发明人： Syuji Takada , Yasuhiro Ooba
IPC分类号： G06F1200
CPC分类号： H04L12/5601 , H04L47/50 , H04L47/56 , H04L49/90 , H04L49/901 , H04L49/9094 , H04L2012/5625 , H04L2012/5651 , H04L2012/5652 , H04L2012/5681 , H04Q11/0478
摘要： In data insertion control technique; a plurality of buffers hold different types of data, which are to be inserted into a predetermined transmission medium and are equal in insertion priority, and a data insertion controller controls the data insertion order in which the data are to be inserted into the transmission medium by controlling the read process order in which the different types of data are to read from the buffers, based on the write process order in which the different types of data have been stored in the buffers. The result is that it is possible to realize exact data insertion in a minimum delay time.
摘要翻译：数据插入控制技术; 多个缓冲器保存要插入到预定传输介质中并且插入优先级相等的不同类型的数据，并且数据插入控制器通过以下方式控制数据插入顺序，其中数据将被插入到传输介质中基于不同类型的数据已经存储在缓冲器中的写入处理顺序来控制从缓冲器读取不同类型的数据的读取处理顺序。结果是可以在最小延迟时间内实现准确的数据插入。

9. 发明授权

US07978704B2 Frame buffer monitoring method and device 有权
标题翻译：帧缓冲区监控方法和设备
公开(公告)号：US07978704B2
公开(公告)日：2011-07-12
申请号：US11443243
申请日：2006-05-31
申请人： Shiuji Sakakura , Yasuhiro Ooba , Yukio Suda , Masayuki Horie
发明人： Shiuji Sakakura , Yasuhiro Ooba , Yukio Suda , Masayuki Horie
IPC分类号： H04L12/28
CPC分类号： H04L49/555 , H04L49/30
摘要： In a frame buffer monitoring method and device, information concerning a received frame is extracted, and a monitoring frame added to a start of the frame is written in a FIFO buffer. When the monitoring frame is read from the FIFO buffer, expectation information is generated from the information concerning the frame added to the start of the monitoring frame read, the expectation information is compared with the information concerning the frame included in the frame within the monitoring frame read, and whether or not the expectation information is consistent with the information concerning the frame is determined. As a result of the comparison, when it is determined that the expectation information is not consistent with the information concerning the frame, e.g. bits of an FCS within the frame which is determined to be inconsistent are inverted to be transmitted to a subsequent stage as a discarded frame or the frame is discarded. Also, a write destination address and a read source address for the FIFO buffer are initialized.
摘要翻译：在帧缓冲器监视方法和装置中，提取关于接收到的帧的信息，并且将添加到帧的开始的监视帧写入FIFO缓冲器。当从FIFO缓冲器读取监视帧时，根据从读取的监视帧开始的相关信息产生预期信息，将期望信息与监视帧内的帧中包含的帧的信息进行比较读取，以及期望信息是否与关于帧的信息一致。作为比较的结果，当确定期望信息与关于帧的信息不一致时，例如，被确定为不一致的帧内的FCS的比特被反转以作为丢弃的帧被发送到后一级，或者丢弃该帧。此外，初始化FIFO缓冲器的写目的地地址和读源地址。

10. 发明申请

US20070189314A1 Frame buffer monitoring method and device 有权
标题翻译：帧缓冲区监控方法和设备
公开(公告)号：US20070189314A1
公开(公告)日：2007-08-16
申请号：US11443243
申请日：2006-05-31
申请人： Shiuji Sakakura , Yasuhiro Ooba , Yukio Suda , Masayuki Horie
发明人： Shiuji Sakakura , Yasuhiro Ooba , Yukio Suda , Masayuki Horie
IPC分类号： H04L12/56
CPC分类号： H04L49/555 , H04L49/30
摘要： In a frame buffer monitoring method and device, information concerning a received frame is extracted, and a monitoring frame added to a start of the frame is written in a FIFO buffer. When the monitoring frame is read from the FIFO buffer, expectation information is generated from the information concerning the frame added to the start of the monitoring frame read, the expectation information is compared with the information concerning the frame included in the frame within the monitoring frame read, and whether or not the expectation information is consistent with the information concerning the frame is determined. As a result of the comparison, when it is determined that the expectation information is not consistent with the information concerning the frame, e.g. bits of an FCS within the frame which is determined to be inconsistent are inverted to be transmitted to a subsequent stage as a discarded frame or the frame is discarded. Also, a write destination address and a read source address for the FIFO buffer are initialized.
摘要翻译：在帧缓冲器监视方法和装置中，提取关于接收到的帧的信息，并且将添加到帧的开始的监视帧写入FIFO缓冲器。当从FIFO缓冲器读取监视帧时，根据从读取的监视帧开始的相关信息产生预期信息，将期望信息与监视帧内的帧中包含的帧的信息进行比较读取，以及期望信息是否与关于帧的信息一致。作为比较的结果，当确定期望信息与关于帧的信息不一致时，例如，被确定为不一致的帧内的FCS的比特被反转以作为丢弃的帧被发送到后一级，或者丢弃该帧。此外，初始化FIFO缓冲器的写目的地地址和读源地址。

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