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1. 发明申请

US20100114543A1 SIMULATION METHOD FOR TRANSISTOR UNSUITABLE FOR EXISTING MODEL 有权
标题翻译：用于现有模型的晶体管的仿真方法
公开(公告)号：US20100114543A1
公开(公告)日：2010-05-06
申请号：US12608551
申请日：2009-10-29
申请人： Yasuhiro NAMBA , Peter Lee
发明人： Yasuhiro NAMBA , Peter Lee
IPC分类号： G06G7/48
CPC分类号： G06F17/5036
摘要： A simulation method includes determining a relationship between stress time and a degradation rate of drain current on a basis of a table in which data of a lifetime of a transistor, or the degradation rate of the transistor, is written, and calculating an amount of change in drain current accordance with the degradation rate, using a table in which information indicating a change in the drain current, being dependent on voltage, is written, based on actually measured data of drain current of the transistor after degradation, drain current in an initial state of a particular transistor model, and the relationship between stress time and the degradation rate of drain current.
摘要翻译：模拟方法包括基于其中写入晶体管的寿命数据或晶体管的劣化速率的数据的表来确定应力时间和漏极电流的劣化率之间的关系，并计算变化量在根据劣化率的漏极电流中，使用其中写入表示依赖于电压的漏极电流的变化的信息的表，基于在劣化后晶体管的漏极电流的实际测量数据，初始的漏极电流特定晶体管模型的状态，以及应力时间与漏极电流的劣化率之间的关系。

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