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1. 发明申请

US20120262885A1 SIGNAL TRANSFER CIRCUIT 审中-公开
标题翻译：信号传输电路
公开(公告)号：US20120262885A1
公开(公告)日：2012-10-18
申请号：US13358540
申请日：2012-01-26
申请人： Yasuhiro IKEDA , Yutaka Uematsu , Satoshi Muraoka
发明人： Yasuhiro IKEDA , Yutaka Uematsu , Satoshi Muraoka
IPC分类号： H05K1/18
CPC分类号： H05K1/0243 , H05K1/0251 , H05K1/115 , H05K2201/09227 , H05K2201/09772 , H05K2201/10545 , H05K2201/10689
摘要： Provided is a signal transfer circuit which uses a low cost circuit board with a high packing density but is capable of reducing a crosstalk noise between signal lines and also reducing a reflection noise due to a stub. A signal transfer circuit of the present invention is configured such that lead terminals of electronic components and through-hole vias are connected to each other by surface wirings, respectively, to allow no branching from the middle of the through-hole vias. Further, first wirings connecting a first electronic component are each arranged between a corresponding pair of second wirings connecting a second electronic component, and signals are transmitted through the first wirings and the second wirings by interleaved transmission.
摘要翻译：提供了一种使用具有高包装密度的低成本电路板的信号传输电路，但是能够减少信号线之间的串扰噪声并且还减少由于短截线引起的反射噪声。本发明的信号传输电路被配置为使得电子部件和通孔过孔的引线端子分别通过表面布线彼此连接，以便不允许从通孔过孔的中间分支。此外，连接第一电子部件的第一布线分别布置在连接第二电子部件的相应的一对第二布线之间，并且信号通过交错传输通过第一布线和第二布线传输。

2. 发明申请

US20120112849A1 DATA TRANSMISSION SYSTEM AND SEMICONDUCTOR CIRCUIT 有权
标题翻译：数据传输系统和半导体电路
公开(公告)号：US20120112849A1
公开(公告)日：2012-05-10
申请号：US13004609
申请日：2011-01-11
申请人： Yasuhiro IKEDA , Yutaka UEMATSU , Satoshi MURAOKA
发明人： Yasuhiro IKEDA , Yutaka UEMATSU , Satoshi MURAOKA
IPC分类号： H03H2/00 , H03H7/38
CPC分类号： H04B3/02
摘要： A data transmission system is provided in which it is possible to perform both of suppressing the degrading of the slew rate and suppressing the ringing even if load capacitance of an input buffer is changed.The data transmission system transmitting data from an output buffer to the input buffer through a trace is provided with first RC parallel circuits connected in series to the trace on a first Printed Circuit Board (PCB) on which the output buffer is mounted, and second RC parallel circuits connected in series to the trace on a second Printed Circuit Board (PCB) on which the input buffer is mounted, and which can be connected and separated to and from the first Printed Circuit Board (PCB).
摘要翻译：提供了一种数据传输系统，其中即使输入缓冲器的负载电容改变，也可以同时执行抑制转换速率的降级和抑制振铃的两者。通过轨迹将数据从输出缓冲器传输到输入缓冲器的数据传输系统提供有与其上安装有输出缓冲器的第一印刷电路板（PCB）上的迹线串联连接的第一RC并联电路，以及第二RC 并联电路与安装有输入缓冲器的第二印刷电路板（PCB）上的迹线串联连接，并且可以与第一个印刷电路板（PCB）连接和分离。

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