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1. 发明授权

US08008948B2 Peak voltage detector circuit and binarizing circuit including the same circuit 有权
标题翻译：峰值电压检测电路和二值化电路包括相同电路
公开(公告)号：US08008948B2
公开(公告)日：2011-08-30
申请号：US12000304
申请日：2007-12-11
申请人： Yasuaki Makino , Hiroshi Okada , Reiji Iwamoto , Nobukazu Oba , Shinji Nakatani , Norikazu Ohta , Hideki Hosokawa
发明人： Yasuaki Makino , Hiroshi Okada , Reiji Iwamoto , Nobukazu Oba , Shinji Nakatani , Norikazu Ohta , Hideki Hosokawa
IPC分类号： G01R19/00 , G06M1/10
CPC分类号： G01R19/04
摘要： A peak voltage detector circuit detects a peak voltage of an input voltage. The input voltage is input into a first input terminal of a comparator. A counter circuit counts up a counter value in synchronization with a first clock signal, when a signal output from the comparator is in a first state. The counter circuit counts down the counter value in synchronization with a second clock signal. A digital-analog conversion circuit outputs an output voltage corresponding to the counter value, and the output voltage is input into a second input terminal of the comparator. The first clock signal has a wave period shorter than that of the second clock signal.
摘要翻译：峰值电压检测电路检测输入电压的峰值电压。输入电压被输入到比较器的第一输入端。当从比较器输出的信号处于第一状态时，计数器电路与第一时钟信号同步地计数计数器值。计数器电路与第二个时钟信号同步地计数计数器值。数字模拟转换电路输出对应于计数器值的输出电压，输出电压被输入到比较器的第二输入端。第一时钟信号具有比第二时钟信号短的波周期。

2. 发明申请

US20080211544A1 Peak voltage detector circuit and binarizing circuit including the same circuit 有权
公开(公告)号：US20080211544A1
公开(公告)日：2008-09-04
申请号：US12000304
申请日：2007-12-11
申请人： Yasuaki Makino , Hiroshi Okada , Reiji Iwamoto , Nobukazu Oba , Shinji Nakatani , Norikazu Ohta , Hideki Hosokawa
发明人： Yasuaki Makino , Hiroshi Okada , Reiji Iwamoto , Nobukazu Oba , Shinji Nakatani , Norikazu Ohta , Hideki Hosokawa
IPC分类号： H03K5/1532
CPC分类号： G01R19/04
摘要： A peak voltage detector circuit detects a peak voltage of an input voltage. The input voltage is input into a first input terminal of a comparator. A counter circuit counts up a counter value in synchronization with a first clock signal, when a signal output from the comparator is in a first state. The counter circuit counts down the counter value in synchronization with a second clock signal. A digital-analog conversion circuit outputs an output voltage corresponding to the counter value, and the output voltage is input into a second input terminal of the comparator. The first clock signal has a wave period shorter than that of the second clock signal.

3. 发明申请

US20070285291A1 Binarization circuit 审中-公开
标题翻译：二元化电路
公开(公告)号：US20070285291A1
公开(公告)日：2007-12-13
申请号：US11717169
申请日：2007-03-13
申请人： Yasuaki Makino , Susumu Kuroyanagi , Shinji Nakatani , Reiji Iwamoto , Hideki Hosokawa , Norikazu Ohta
发明人： Yasuaki Makino , Susumu Kuroyanagi , Shinji Nakatani , Reiji Iwamoto , Hideki Hosokawa , Norikazu Ohta
IPC分类号： H03M1/12
CPC分类号： H03K5/003 , H03K3/3565 , H03K5/084 , H04L25/063
摘要： A binarization circuit for binarizing a pulsative analog signal includes: a first comparator circuit for reversing an output signal when the analog signal becomes smaller than a threshold voltage and when the analog signal becomes larger than a high side threshold voltage; a second comparator circuit for reversing an output signal when the analog signal becomes larger than the threshold voltage and when the analog signal becomes smaller than a low side threshold voltage; and a selector circuit for inputting the output signals from the first and second comparator circuits and for reversing an output signal when the analog signal becomes smaller than the threshold voltage and when the analog signal becomes larger than the threshold voltage.
摘要翻译：用于二值化脉冲模拟信号的二值化电路包括：第一比较器电路，用于当模拟信号变得小于阈值电压时以及当模拟信号变得大于高侧阈值电压时反转输出信号; 第二比较器电路，用于当模拟信号变得大于阈值电压时以及当模拟信号变得小于低侧阈值电压时反转输出信号; 以及选择器电路，用于输入来自第一和第二比较器电路的输出信号，并且当模拟信号变得小于阈值电压时以及当模拟信号变得大于阈值电压时反转输出信号。

4. 发明申请

US20080048641A1 Peak voltage detector circuit and binarizing circuit including the same circuit 审中-公开
标题翻译：峰值电压检测电路和二值化电路包括相同电路
公开(公告)号：US20080048641A1
公开(公告)日：2008-02-28
申请号：US11822291
申请日：2007-07-03
申请人： Yasuaki Makino , Hiroshi Okada , Reiji Iwamoto , Norikazu Ohta , Hideki Hosokawa
发明人： Yasuaki Makino , Hiroshi Okada , Reiji Iwamoto , Norikazu Ohta , Hideki Hosokawa
IPC分类号： G01R19/04
CPC分类号： G01R19/04
摘要： A peak voltage detector circuit detects a peak voltage of an input voltage. The input voltage is input into a first input terminal of a comparator. A counter circuit counts up a counter value in synchronization with a first clock signal, when a signal output from the comparator is in a first state. The counter circuit counts down the counter value in synchronization with a second clock signal. A digital-analog conversion circuit outputs an output voltage corresponding to the counter value, and the output voltage is input into a second input terminal of the comparator. The first clock signal has a wave period shorter than that of the second clock signal.
摘要翻译：峰值电压检测电路检测输入电压的峰值电压。输入电压被输入到比较器的第一输入端。当从比较器输出的信号处于第一状态时，计数器电路与第一时钟信号同步地计数计数器值。计数器电路与第二个时钟信号同步地计数计数器值。数字模拟转换电路输出对应于计数器值的输出电压，输出电压被输入到比较器的第二输入端。第一时钟信号具有比第二时钟信号短的波周期。

5. 发明授权

US06809527B2 METHOD OF MEASURING A CHARACTERISTIC OF A CAPACITIVE TYPE OF SENSOR, A SENSOR CHARACTERISTIC MEASURING APPARATUS, A CAPACITIVE TYPE OF SENSOR APPARATUS, AND AN IC CHIP FOR MEASURING A SENSOR CHARACTERISTIC 有权
标题翻译：测量传感器电容式特性的方法，传感器特性测量装置，传感器装置的电容型和用于测量传感器特性的IC芯片
公开(公告)号：US06809527B2
公开(公告)日：2004-10-26
申请号：US10189599
申请日：2002-07-08
申请人： Seiichiro Ishio , Yasutoshi Suzuki , Hajime Ito , Yasuaki Makino , Norikazu Ohta , Keiichi Shimaoka , Hirofumi Funahashi
发明人： Seiichiro Ishio , Yasutoshi Suzuki , Hajime Ito , Yasuaki Makino , Norikazu Ohta , Keiichi Shimaoka , Hirofumi Funahashi
IPC分类号： G01R2726
CPC分类号： G01R27/2605
摘要： First and second predetermined charging voltages are applied between the movable and fixed electrodes of a capacitive type of sensor to measure first and second capacitances between the movable and fixed electrodes, respectively. The first and second electrostatic capacitances are compared to obtain a characteristic of the sensor from a result of comparison. In measuring the first and second capacitances, first and second charging voltages are generated of which magnitudes are determined in accordance with the first and second capacitances, respectively. Equalization is made between the first output voltage when the first charging voltage is applied between the movable and fixed electrodes in a predetermined normal condition of the movable electrode and the second output voltage outputted when the second charging voltage is applied between the movable and fixed electrodes in the predetermined normal condition.
摘要翻译：第一和第二预定充电电压被施加在电容式传感器的可移动和固定电极之间，以分别测量可移动和固定电极之间的第一和第二电容。比较第一和第二静电电容，以从比较结果获得传感器的特性。在测量第一和第二电容时，分别产生根据第一和第二电容确定幅度的第一和第二充电电压。在第一充电电压在可动电极的预定正常状态下施加于可动电极与固定电极之间的第一输出电压和在可动电极和固定电极之间施加第二充电电压时输出的第二输出电压之间进行均衡预定的正常状态。

6. 发明授权

US07560998B2 Clock signal output circuit 有权
标题翻译：时钟信号输出电路
公开(公告)号：US07560998B2
公开(公告)日：2009-07-14
申请号：US11604198
申请日：2006-11-27
申请人： Norikazu Ohta , Yoshie Ohira , Yasuaki Makino , Hiromi Ariyoshi
发明人： Norikazu Ohta , Yoshie Ohira , Yasuaki Makino , Hiromi Ariyoshi
IPC分类号： H03K3/03 , H03L1/00
CPC分类号： H03K3/354 , H03K3/0315 , H03K2005/0013 , H03K2005/00143 , H03K2005/00169
摘要： 1st to nth pairs of transistors (n=an odd number) are connected in parallel, and each pair of transistors has an upper transistor and a lower transistor connected in series. A point between the upper transistor and the lower transistor of a preceding pair of transistors is connected to a gate of the lower transistor of a subsequent transistor, and the point between the upper transistor and the lower transistor of nth pair of transistors is connected to the gate of the first lower transistor. A capacitor is inserted between the lower transistor and a direct power source. A current regulating circuit connected to gates of the upper transistors, wherein the current regulating circuit supplies a gate voltage to each gate of the each upper transistor. The magnitude of the gate voltage is adjusted such that a magnitude of current that flows between the source and drain of the upper transistor due to the gate voltage is proportional to a voltage between the source and gate of the corresponding lower transistor when the lower transistor is turned on.
摘要翻译：第一至第n对晶体管（n =奇数）并联连接，并且每对晶体管具有串联连接的上晶体管和下晶体管。前一对晶体管的上晶体管和下晶体管之间的点连接到后续晶体管的下晶体管的栅极，并且第n对晶体管的上晶体管和下晶体管之间的点连接到第一低级晶体管的栅极。电容器插在下晶体管和直接电源之间。连接到上部晶体管的栅极的电流调节电路，其中电流调节电路向每个上部晶体管的每个栅极提供栅极电压。调整栅极电压的大小，使得由于栅极电压而在上部晶体管的源极和漏极之间流动的电流的大小与当下部晶体管为相应的下部晶体管的源极和栅极之间的电压成比例时打开。

7. 发明申请

US20060176043A1 Reference voltage circuit 有权
标题翻译：参考电压电路
公开(公告)号：US20060176043A1
公开(公告)日：2006-08-10
申请号：US11311182
申请日：2005-12-20
申请人： Yasuaki Makino , Norikazu Ohta , Yoshie Ohira , Hirofumi Funabashi
发明人： Yasuaki Makino , Norikazu Ohta , Yoshie Ohira , Hirofumi Funabashi
IPC分类号： G05F3/04 , G05F3/08
CPC分类号： G05F3/30
摘要： A reference voltage circuit includes an operational amplifier, a first fixed resistance resistor, a second fixed resistance resistor, a third fixed resistance resistor, a first diode and a second diode. The reference voltage circuit further includes a fourth fixed resistance resistor having an end connected to a non-inverting input terminal of the operational amplifier and the other end connected to the first diode. The reference voltage circuit is characterized by a value of the resistance of the fourth resistor being less than the resistance of the first resistor and a temperature coefficient of the fourth resistor being greater than any of the temperature coefficients of the first, second and third resistors.
摘要翻译：参考电压电路包括运算放大器，第一固定电阻电阻，第二固定电阻电阻，第三固定电阻电阻，第一二极管和第二二极管。参考电压电路还包括第四固定电阻电阻器，其端部连接到运算放大器的非反相输入端子，另一端连接到第一二极管。参考电压电路的特征在于第四电阻器的电阻小于第一电阻器的电阻值，第四电阻器的温度系数大于第一，第二和第三电阻器的任何温度系数。

8. 发明申请

US20070146072A1 Clock signal output circuit 有权
标题翻译：时钟信号输出电路
公开(公告)号：US20070146072A1
公开(公告)日：2007-06-28
申请号：US11604198
申请日：2006-11-27
申请人： Norikazu Ohta , Yoshie Ohira , Yasuaki Makino , Hiromi Ariyoshi
发明人： Norikazu Ohta , Yoshie Ohira , Yasuaki Makino , Hiromi Ariyoshi
IPC分类号： H03F3/45
CPC分类号： H03K3/354 , H03K3/0315 , H03K2005/0013 , H03K2005/00143 , H03K2005/00169
摘要： 1st to nth pairs of transistors (n=an odd number) are connected in parallel, and each pair of transistors has an upper transistor and a lower transistor connected in series. A point between the upper transistor and the lower transistor of a preceding pair of transistors is connected to a gate of the lower transistor of a subsequent transistor, and the point between the upper transistor and the lower transistor of nth pair of transistors is connected to the gate of the first lower transistor. A capacitor is inserted between the lower transistor and a direct power source. A current regulating circuit connected to gates of the upper transistors, wherein the current regulating circuit supplies a gate voltage to each gate of the each upper transistor. The magnitude of the gate voltage is adjusted such that a magnitude of current that flows between the source and drain of the upper transistor due to the gate voltage is proportional to a voltage between the source and gate of the corresponding lower transistor when the lower transistor is turned on.
摘要翻译：并联连接第n个第n个（n =奇数）对的第一个第一和第二个晶体管，每对晶体管具有串联连接的上部晶体管和下部晶体管。先前一对晶体管的上部晶体管和下部晶体管之间的点连接到后续晶体管的下部晶体管的栅极，并且上部晶体管和下部晶体管之间的点位于第n / >一对晶体管连接到第一下晶体管的栅极。电容器插在下晶体管和直接电源之间。连接到上部晶体管的栅极的电流调节电路，其中电流调节电路向每个上部晶体管的每个栅极提供栅极电压。调整栅极电压的大小，使得由于栅极电压而在上部晶体管的源极和漏极之间流动的电流的大小与当下部晶体管为相应的下部晶体管的源极和栅极之间的电压成比例时打开。

9. 发明授权

US07233136B2 Circuit for outputting stable reference voltage against variation of background temperature or variation of voltage of power source 有权
标题翻译：用于输出稳定的参考电压的电路，以抵抗背景温度的变化或电源电压的变化
公开(公告)号：US07233136B2
公开(公告)日：2007-06-19
申请号：US11311182
申请日：2005-12-20
申请人： Yasuaki Makino , Norikazu Ohta , Yoshie Ohira , Hirofumi Funabashi
发明人： Yasuaki Makino , Norikazu Ohta , Yoshie Ohira , Hirofumi Funabashi
IPC分类号： G05F3/16 , G05F3/20
CPC分类号： G05F3/30
摘要： A reference voltage circuit includes an operational amplifier, a first fixed resistance resistor, a second fixed resistance resistor, a third fixed resistance resistor, a first diode and a second diode. The reference voltage circuit further includes a fourth fixed resistance resistor having an end connected to a non-inverting input terminal of the operational amplifier and the other end connected to the first diode. The reference voltage circuit is characterized by a value of the resistance of the fourth resistor being less than the resistance of the first resistor and a temperature coefficient of the fourth resistor being greater than any of the temperature coefficients of the first, second and third resistors.
摘要翻译：参考电压电路包括运算放大器，第一固定电阻电阻，第二固定电阻电阻，第三固定电阻电阻，第一二极管和第二二极管。参考电压电路还包括第四固定电阻电阻器，其端部连接到运算放大器的非反相输入端子，另一端连接到第一二极管。参考电压电路的特征在于第四电阻器的电阻小于第一电阻器的电阻值，第四电阻器的温度系数大于第一，第二和第三电阻器的任何温度系数。

10. 发明授权

US06744258B2 Capacitive sensor apparatus 有权
标题翻译：电容传感器装置
公开(公告)号：US06744258B2
公开(公告)日：2004-06-01
申请号：US10189565
申请日：2002-07-08
申请人： Seiichiro Ishio , Yasutoshi Suzuki , Hajime Ito , Yasuaki Makino , Norikazu Ohta , Keiichi Shimaoka , Hirofumi Funabashi
发明人： Seiichiro Ishio , Yasutoshi Suzuki , Hajime Ito , Yasuaki Makino , Norikazu Ohta , Keiichi Shimaoka , Hirofumi Funabashi
IPC分类号： G01R3112
CPC分类号： G01D3/08
摘要： In a capacitive sensor apparatus, a capacitive sensor includes a plurality of physical-quantity-detection capacitors each having a movable electrode and a fixed electrode. A conversion device operates for converting an output signal of the capacitive sensor into an apparatus output signal. Each of the physical-quantity-detection capacitors is selectively connected and disconnected to and from the conversion device. A determination is made as to whether or not each of the physical-quantity-detection capacitors fails in response to the sensor output signal. When it is determined that a first one of the physical-quantity-detection capacitors fails, the first one is disconnected from the conversion device and a second one of the physical-quantity-detection capacitors is connected to the conversion device.
摘要翻译：在电容传感器装置中，电容式传感器包括多个物理量检测电容器，每个物理量检测电容器具有可动电极和固定电极。转换装置用于将电容式传感器的输出信号转换成装置输出信号。每个物理量检测电容器被选择性地连接到转换装置和从转换装置断开。确定每个物理量检测电容器是否响应于传感器输出信号而失败。当确定物理量检测电容器中的第一个电容器发生故障时，第一个物理量检测电容器与转换装置断开连接，并且第二个物理量检测电容器连接到转换装置。

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